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PDF ISL22444 Data sheet ( Hoja de datos )
| Número de pieza | ISL22444 | |
| Descripción | Quad Digitally Controlled Potentiometer | |
| Fabricantes | Intersil | |
| Logotipo |  |
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NOT RECOMMENDED FOR NEW DESIGNS
RECOMMENDED REPLACEMENT PART
ISL22424
ISL22444
Quad Digitally Controlled Potentiometer (XDCP™)
Data Sheet
May 24, 2007
FN6426.0
Low Noise, Low Power, SPI® Bus, 256 Taps
The ISL22444 integrates four digitally controlled
potentiometers (DCP), control logic and non-volatile memory
on a monolithic CMOS integrated circuit.
The digitally controlled potentiometers are implemented with
a combination of resistor elements and CMOS switches. The
wipers position is controlled by the user through the SPI
serial interface. Each potentiometer has an associated
volatile Wiper Register (WRi) and a non-volatile Initial Value
Register (IVRi) that can be directly written to and read by the
user. The contents of the WRi control the position of the
wiper. At power-up the device recalls the contents of the
DCP’s IVRi to the corresponding WRi.
The ISL22444 also has 11 General Purpose non-volatile
registers that can be used as storage of lookup table for
multiple wiper position or any other valuable information.
The ISL22444 features a dual supply that is beneficial for
applications requiring a bipolar range for DCP terminals
between V- and VCC.
Each DCP can be used as three-terminal potentiometer or
as two-terminal variable resistor in a wide variety of
applications including control, parameter adjustments, and
signal processing.
Features
• Four potentiometers in one package
• 256 resistor taps
• SPI serial interface with write/read capability
• Daisy Chain Configuration
• Shutdown mode
• Non-volatile EEPROM storage of wiper position
• 11 General Purpose non-volatile registers
• High reliability
- Endurance: 1,000,000 data changes per bit per register
- Register data retention: 50 years @ T 55°C
• Wiper resistance: 70 typical @ 1mA
• Standby current <4µA max
• Shutdown current <4µA max
• Dual power supply
- VCC = 2.25V to 5.5V
- V- = -2.25V to -5.5V
• 10k 50kor 100k total resistance
• Extended industrial temperature range: -40 to +125°C
• 20 Ld TSSOP or 20 Ld QFN
• Pb-free plus anneal product (RoHS compliant)
Ordering Information
PART NUMBER
(Notes 1, 2)
ISL22444TFV20Z
PART MARKING
22444 TFVZ
RESISTANCE
OPTION (k)
100
TEMPERATURE
RANGE (°C)
-40 to +125
PACKAGE
(Pb-free)
20 Ld TSSOP
PKG. DWG. #
M20.173
ISL22444TFR20Z
22444 TFRZ
100
-40 to +125
20 Ld QFN
L20.5x5
ISL22444UFV20Z
22444 UFVZ
50
-40 to +125
20 Ld TSSOP
M20.173
ISL22444UFR20Z
22444 UFRZ
50
-40 to +125
20 Ld QFN
L20.5x5
ISL22444WFV20Z
22444 WFVZ
10
-40 to +125
20 Ld TSSOP
M20.173
ISL22444WFR20Z
22444 WFRZ
10
-40 to +125
20 Ld QFN
L20.5x5
NOTES:
1. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2. Add “-TK” suffix for 1,000 Tape and Reel option
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) and XDCP are registered trademarks of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL22444
Analog Specifications Over recommended operating conditions unless otherwise stated. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
TYP
MIN (NOTE 4) MAX
fcutoff
-3dB cut off frequency
(Note 20)
Wiper at midpoint (80hex) W option (10k)
Wiper at midpoint (80hex) U option (50k)
1000
250
Wiper at midpoint (80hex) T option (100k)
120
RESISTOR MODE (Measurements between RWi and RL i with RHi not connected, or between RWi and RHi with RLi not connected)
RINL
Integral non-linearity
(Note 15)
W option
-3 ±1.5
3
U, T option
-1 ±0.4
1
RDNL Differential non-linearity
(Note 14)
W option
U, T option
-1.5 ±0.5
1.5
-0.5 ±0.15 0.5
Roffset Offset
(Note 13)
W option
U, T option
015
0 0.5 2
RMATCH DCP to DCP matching
(Note 16)
Wipers at the same tap position with the
same terminal voltages
-3
3
TCR Resistance temperature coefficient
(Note 17, 20)
DCP register set between 32 hex and FFhex
±40
UNIT
kHz
kHz
kHz
MI
(Note 12)
MI
(Note 12)
MI
(Note 12)
MI
(Note 12)
MI
(Note 12)
MI
(Note 12)
MI
(Note 12)
ppm/°C
Operating Specifications Over the recommended operating conditions unless otherwise specified.
SYMBOL
ICC1
PARAMETER
VCC Supply Current (volatile
write/read)
IV-1 V- Supply Current (volatile
write/read)
ICC2
VCC Supply Current (non-volatile
write/read)
IV-2 V- Supply Current (non-volatile
write/read)
V- Supply Current (non-volatile
write/read)
ISB VCC Current (standby)
TEST CONDITIONS
VCC = 5.5V, fSCK = 5MHz; (for SPI Active, Read
and Volatile Write states only)
VCC = 2.25V, fSCK = 5MHz; (for SPI Active, Read
and Volatile Write states only)
V- = -5.5V, VCC = 5.5V, fSCK = 5MHz; (for SPI
Active, Read and Volatile Write states only)
V- = -2.25V, VCC = 2.25V, fSCK = 5MHz; (for SPI
Active, Read and Volatile Write states only)
VCC = 5.5V, V- = 5.5V, fSCK = 5MHz; (for SPI
Active, Read and Non-volatile Write states only)
VCC = 2.25V, V- = -2.25V, fSCK = 5MHz; (for SPI
Active, Read and Non-volatile Write states only)
V- = -5.5V, VCC = 5.5V, fSCK = 5MHz; (for SPI
Active, Read and Non-volatile Write states only)
V- = -2.25V, VCC = 2.25V, fSCK = 5MHz; (for SPI
Active, Read and Non-volatile Write states only)
VCC = +5.5V, V- = -5.5V @ +85°C, SPI interface
in standby state
VCC = +5.5V, V- = -5.5V @ +125°C, SPI interface
in standby state
VCC = +2.25V, V- = -2.25V @ +85°C, SPI
interface in standby state
VCC = +2.25V, V- = -2.25V @ +125°C, SPI
interface in standby state
MIN
-1.0
-0.5
-2.0
-1.0
TYP
(NOTE 4)
0.6
MAX
1.0
0.25 0.5
-0.3
-0.1
1.0 2.0
0.3 1.0
-1.2
-0.4
0.5 2.0
1.0 4.0
0.2 1.0
0.5 2.0
UNIT
mA
mA
mA
mA
mA
mA
mA
mA
µA
µA
µA
µA
5 FN6426.0
May 24, 2007
5 Page 
ISL22444
Typical Performance Curves (Continued)
SCL
CS
WIPER
WIPER UNLOADED,
MOVEMENT FROM 0h to FFh
FIGURE 13. MIDSCALE GLITCH, CODE 7Fh TO 80h
Pin Description
Potentiometer Pins
RHI AND RLI
The high (RHi) and low (RLi) terminals of the ISL22444 are
equivalent to the fixed terminals of a mechanical
potentiometer. RHi and RLi are referenced to the relative
position of the wiper and not the voltage potential on the
terminals. With WRi set to 255 decimal, the wiper will be
closest to RHi, and with the WRi set to 0, the wiper is closest
to RLi.
RWI
RWi is the wiper terminal and is equivalent to the movable
terminal of a mechanical potentiometer. The position of the
wiper within the array is determined by the WRi register.
Bus Interface Pins
SERIAL CLOCK (SCK)
This is the serial clock input of the SPI serial interface.
SERIAL DATA OUTPUT (SDO)
The SDO is a serial data output pin. During a read cycle, the
data bits are shifted out on the falling edge of the serial clock
SCK and will be available to the master on the following
rising edge of SCK.
The output type is configured through ACR[1] bit for Push-
Pull or Open Drain operation. Default setting for this pin is
Push-Pull. An external pull up resistor is required for Open
Drain output operation. Note: the external pull up voltage not
allowed beyond VCC.
SERIAL DATA INPUT (SDI)
The SDI is the serial data input pin for the SPI interface. It
receives device address, operation code, wiper address and
data from the SPI remote host device. The data bits are
11
FIGURE 14. LARGE SIGNAL SETTLING TIME
shifted in at the rising edge of the serial clock SCK, while the
CS input is low.
CHIP SELECT (CS)
CS LOW enables the ISL22444, placing it in the active
power mode. A HIGH to LOW transition on CS is required
prior to the start of any operation after power up. When CS is
HIGH, the ISL22444 is deselected and the SDO pin is at
high impedance, and (unless an internal write cycle is
underway) the device will be in the standby state.
Principles of Operation
The ISL22444 is an integrated circuit incorporating four
DCPs with their associated registers, non-volatile memory
and the SPI serial interface providing direct communication
between host, potentiometers and memory. The resistor
arrays are comprised of individual resistors connected in a
series. At either end of the array and between each resistor
is an electronic switch that transfers the potential at that
point to the wiper.
The electronic switches on the device operate in a “make
before break” mode when the wiper changes tap positions.
When the device is powered down, the last value stored in
IVRi will be maintained in the non-volatile memory. When
power is restored, the content of the IVRi is recalled and
loaded into the corresponding WRi to set the wiper to the
initial position.
DCP Description
Each DCP is implemented with a combination of resistor
elements and CMOS switches. The physical ends of each
DCP are equivalent to the fixed terminals of a mechanical
potentiometer (RHi and RLi pins). The RWi pin of the DCP is
connected to intermediate nodes, and is equivalent to the
wiper terminal of a mechanical potentiometer. The position
of the wiper terminal within the DCP is controlled by an 8-bit
volatile Wiper Register (WRi). When the WRi of a DCP
FN6426.0
May 24, 2007
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet ISL22444.PDF ] | |
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