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S34MS08G2 の電気的特性と機能

S34MS08G2のメーカーはCypress Semiconductorです、この部品の機能は「NAND Flash Memory」です。


製品の詳細 ( Datasheet PDF )

部品番号 S34MS08G2
部品説明 NAND Flash Memory
メーカ Cypress Semiconductor
ロゴ Cypress Semiconductor ロゴ 




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S34MS08G2 Datasheet, S34MS08G2 PDF,ピン配置, 機能
S34MS08G2
8 Gb, 4-Bit ECC, x8 I/O and 1.8 V VCC
NAND Flash Memory for Embedded
Distinctive Characteristics
Density
– 8 Gb (4 Gb x 2)
Architecture (For each 4 Gb device)
– Input / Output Bus Width: 8-bits
– Page Size: (2048 + 128) bytes; 128-byte spare area
– Block Size: 64 Pages or (128k + 8k) bytes
– Plane Size
– 2048 Blocks per Plane or (256M + 16M) bytes
– Device Size
– 2 Planes per Device or 512 Mbyte
NAND Flash Interface
– Open NAND Flash Interface (ONFI) 1.0 compliant
– Address, Data and Commands multiplexed
Supply Voltage
– 1.8V device: VCC = 1.7V ~ 1.95V
Security
– One Time Programmable (OTP) area
– Serial number (unique ID)
– Hardware program/erase disabled during power transition
Additional Features
– Supports Multiplane Program and Erase commands
– Supports Copy Back Program
– Supports Multiplane Copy Back Program
– Supports Read Cache
Electronic Signature
– Manufacturer ID: 01h
Operating Temperature
– Industrial: –40 °C to 85 °C
– Industrial Plus: –40 °C to 105 °C
Performance
Page Read / Program
– Random access: 30 µs (Max)
– Sequential access: 45 ns (Min)
– Program time / Multiplane Program time: 300 µs (Typ)
Block Erase / Multiplane Erase
– Block Erase time: 3.5 ms (Typ)
Reliability
– 100,000 Program / Erase cycles (Typ)
(with 4-bit ECC per 528 bytes)
– 10 Year Data retention (Typ)
– Blocks zero and one are valid and will be valid for at least
1000
program-erase cycles with ECC
Package Options
– Lead Free and Low Halogen
– 63-Ball BGA 9 x 11 x 1 mm
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 002-00515 Rev. *E
• San Jose, CA 95134-1709 • 408-943-2600
Revised October 27, 2016

1 Page





S34MS08G2 pdf, ピン配列
S34MS08G2
1. General Description
The Cypress® S34MS08G2 8-Gb NAND is offered in 1.8VCC with x8 I/O interface. This document contains information for the
S34MS08G2 device, which is a dual-die stack of two S34MS04G2 die. For detailed specifications, please refer to the discrete die
data sheet: S34MS01G2_04G2.
2. Connection Diagram
Figure 2.1 63-BGA Contact, x8 Device, Single CE (Top View)
A1 A2
NC NC
A9 A10
NC NC
B1 B9 B10
NC NC NC
C3 C4 C5 C6 C7 C8
WP#
ALE
VSS
CE#
WE#
RB#
D3 D4 D5 D6 D7 D8
VCC
RE#
CLE
NC
NC
NC
E3 E4 E5 E6 E7 E8
NC NC NC NC NC NC
F3 F4 F5 F6 F7 F8
NC NC NC NC VSS NC
G3 G4 G5 G6 G7 G8
NC VCC NC NC NC NC
H3 H4 H5 H6 H7 H8
NC I/O0 NC NC NC Vcc
J3 J4 J5 J6 J7 J8
NC
I/O1
NC
VCC
I/O5
I/O7
K3 K4 K5 K6 K7 K8
VSS I/O2 I/O3 I/O4 I/O6 VSS
L1 L2
NC NC
L9 L10
NC NC
M1 M2
NC NC
M9 M10
NC NC
Note:
1. These pins should be connected to power supply or ground (as designated) following the ONFI specification, however they might not be bonded internally.
Document Number: 002-00515 Rev. *E
Page 3 of 17


3Pages


S34MS08G2 電子部品, 半導体
CE#
W E#
RE#
ALE
CLE
W P#
Figure 4.2 Block Diagram — 1 CE (4 Gb x 8)
IO0~IO7
CE#
WE#
4 Gb x8
R/B#
RE# N A N D F lash
M em o ry#2 VSS
ALE
VCC
CLE
WP#
IO0~IO7
CE#
WE#
R/B#
4 Gb x8
RE# N A N D F lash VSS
ALE M em o ry#1
VCC
CLE
WP#
IO0~IO7
R /B #
VSS
VCC
S34MS08G2
5. Addressing
Table 5.1 Address Cycle Map
Bus Cycle I/O0 I/O1 I/O2 I/O3 I/O4 I/O5
1st / Col. Add. 1
A0 (CA0)
A1 (CA1)
A2 (CA2)
A3 (CA3)
A4 (CA4)
A5 (CA5)
2nd / Col. Add. 2 A8 (CA8)
A9 (CA9) A10 (CA10) A11 (CA11)
Low
Low
3rd / Row Add. 1 A12 (PA0) A13 (PA1) A14 (PA2) A15 (PA3) A16 (PA4) A17 (PA5)
4th / Row Add. 2 A20 (BA1) A21 (BA2) A22 (BA3) A23 (BA4) A24 (BA5) A25 (BA6)
5th / Row Add. 3 (6) A28 (BA9) A29 (BA10) A30 (BA11)
Low
Low
Low
Notes:
1. CAx = Column Address bit.
2. PAx = Page Address bit.
3. PLA0 = Plane Address bit zero.
4. BAx = Block Address bit.
5. Block address concatenated with page address and plane address = actual page address, also known as the row address.
6. A30 for 8 Gb (4 Gb x 2 – DDP) (1CE).
For the address bits, the following rules apply:
A0 - A11: column address in the page
A12 - A17: page address in the block
A18: plane address (for multiplane operations) / block address (for normal operations)
A19 - A30: block address
I/O6
A6 (CA6)
Low
A18 (PLA0)
A26 (BA7)
Low
I/O7
A7 (CA7)
Low
A19 (BA0)
A27 (BA8)
Low
Document Number: 002-00515 Rev. *E
Page 6 of 17

6 Page



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共有リンク

Link :


部品番号部品説明メーカ
S34MS08G2

NAND Flash Memory

Cypress Semiconductor
Cypress Semiconductor


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