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S34ML01G1 の電気的特性と機能

S34ML01G1のメーカーはCypress Semiconductorです、この部品の機能は「3V SLC NAND Flash」です。


製品の詳細 ( Datasheet PDF )

部品番号 S34ML01G1
部品説明 3V SLC NAND Flash
メーカ Cypress Semiconductor
ロゴ Cypress Semiconductor ロゴ 




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S34ML01G1 Datasheet, S34ML01G1 PDF,ピン配置, 機能
Distinctive Characteristics
Density
– 1 Gb/ 2 Gb / 4 Gb
Architecture
– Input / Output Bus Width: 8-bits / 16-bits
– Page size:
– x8 = 2112 (2048 + 64) bytes; 64 bytes is spare area
– x16 = 1056 (1024 + 32) words; 32 words is spare area
– Block size: 64 Pages
– x8 = 128 KB + 4 KB
– x16 = 64k + 2k words
– Plane size:
– 1 Gb / 2 Gb: 1024 Blocks per Plane
x8 = 128 MB + 4 MB
x16 = 64M + 2M words
– 4 Gb: 2048 Blocks per Plane
x8 = 256 MB+ 8 MB
x16 = 128M + 4M words
– Device size:
– 1 Gb: 1 Plane per Device or 128 MB
– 2 Gb: 2 Planes per Device or 256 MB
– 4 Gb: 2 Planes per Device or 512 MB
Performance
Page Read / Program
– Random access: 25 µs (Max)
– Sequential access: 25 ns (Min)
– Program time / Multiplane Program time: 200 µs (Typ)
Block Erase (S34ML01G1)
– Block Erase time: 2.0 ms (Typ)
Block Erase / Multiplane Erase (S34ML02G1, S34ML04G1)
– Block Erase time: 3.5 ms (Typ)
S34ML01G1
S34ML02G1, S34ML04G1
1 Gb, 2 Gb, 4 Gb, 3 V SLC
NAND Flash For Embedded
NAND flash interface
– Open NAND Flash Interface (ONFI) 1.0 compliant
– Address, Data and Commands multiplexed
Supply voltage
– 3.3-V device: Vcc = 2.7 V ~ 3.6 V
Security
– One Time Programmable (OTP) area
– Hardware program/erase disabled during power transition
Additional features
– 2 Gb and 4 Gb parts support Multiplane Program and Erase
commands
– Supports Copy Back Program
– 2 Gb and 4 Gb parts support Multiplane Copy Back Program
– Supports Read Cache
Electronic signature
– Manufacturer ID: 01h
Operating temperature
– Industrial: -40 °C to 85 °C
– Automotive: -40 °C to 105 °C
Reliability
– 100,000 Program / Erase cycles (Typ)
(with 1 bit ECC per 528 bytes (x8) or 264 words (x16))
– 10 Year Data retention (Typ)
– For one plane structure (1-Gb density)
– Block zero is valid and will be valid for at least 1,000 program-
erase cycles with ECC
– For two plane structures (2-Gb and 4-Gb densities)
– Blocks zero and one are valid and will be valid for at least
1,000 program-erase cycles with ECC
Package options
– Lead Free and Low Halogen
– 48-Pin TSOP 12 x 20 x 1.2 mm
– 63-Ball BGA 9 x 11 x 1 mm
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 002-00676 Rev. *S
• San Jose, CA 95134-1709 • 408-943-2600
Revised Wednesday, August 31, 2016

1 Page





S34ML01G1 pdf, ピン配列
S34ML01G1
S34ML02G1, S34ML04G1
1. General Description
The Cypress S34ML01G1, S34ML02G1, and S34ML04G1 series is offered with a 3.3-V VCC power supply, and with ×8 or ×16 I/O
interface. Its NAND cell provides the most cost-effective solution for the solid state mass storage market. The memory is divided into
blocks that can be erased independently so it is possible to preserve valid data while old data is erased. The page size for ×8 is
(2048 + 64 spare) bytes; for ×16 (1024 + 32) words.
Each block can be programmed and erased up to 100,000 cycles with ECC (error correction code) on. To extend the lifetime of
NAND flash devices, the implementation of an ECC is mandatory.
The chip supports CE# don't care function. This function allows the direct download of the code from the NAND flash memory device
by a microcontroller, since the CE# transitions do not stop the read operation.
The devices have a Read Cache feature that improves the read throughput for large files. During cache reading, the devices load
the data in a cache register while the previous data is transferred to the I/O buffers to be read.
Like all other 2-kB page NAND flash devices, a program operation typically writes 2112 bytes (×8), or 1056 words (×16) in 200 µs
and an erase operation can typically be performed in 2 ms (S34ML01G1) on a 128-kB block (×8) or 64-kword block (×16). In
addition, thanks to multiplane architecture, it is possible to program two pages at a time (one per plane) or to erase two blocks at a
time (again, one per plane). The multiplane architecture allows program time to be reduced by 40% and erase time to be reduced by
50%.
In multiplane operations, data in the page can be read out at 25 ns cycle time per byte. The I/O pins serve as the ports for command
and address input as well as data input/output. This interface allows a reduced pin count and easy migration towards different
densities, without any rearrangement of the footprint.
Commands, Data, and Addresses are asynchronously introduced using CE#, WE#, ALE, and CLE control pins.
The on-chip Program/Erase Controller automates all read, program, and erase functions including pulse repetition, where required,
and internal verification and margining of data. A WP# pin is available to provide hardware protection against program and erase
operations.
The output pin R/B# (open drain buffer) signals the status of the device during each operation. It identifies if the program/erase/read
controller is currently active. The use of an open-drain output allows the Ready/Busy pins from several memories to connect to a
single pull-up resistor. In a system with multiple memories the
R/B# pins can be connected all together to provide a global status signal.
The Reprogram function allows the optimization of defective block management — when a Page Program operation fails the data
can be directly programmed in another page inside the same array section without the time consuming serial data insertion phase.
The Copy Back operation automatically executes embedded error detection operation: 1-bit error out of every 528 bytes (×8) or 256
words (×16) can be detected. With this feature it is no longer necessary to use an external mechanism to detect Copy Back
operation errors.
Multiplane Copy Back is also supported. Data read out after Copy Back Read (both for single and multiplane cases) is allowed.
In addition, Cache Program and Multiplane Cache Program operations improve the programing throughput by programing data
using the cache register.
The devices provide two innovative features: Page Reprogram and Multiplane Page Reprogram. The Page Reprogram re-programs
one page. Normally, this operation is performed after a failed Page Program operation. Similarly, the Multiplane Page Reprogram re-
programs two pages in parallel, one per plane. The first page must be in the first plane while the second page must be in the second
plane. The Multiplane Page Reprogram operation is performed after a failed Multiplane Page Program operation. The Page
Reprogram and Multiplane Page Reprogram guarantee improved performance, since data insertion can be omitted during re-
program operations.
Note: The S34ML01G1 device does not support EDC.
Document Number: 002-00676 Rev. *S
Page 3 of 73


3Pages


S34ML01G1 電子部品, 半導体
S34ML01G1
S34ML02G1, S34ML04G1
Figure 1.4 63-BGA Contact, ×16 Device (Balls Down, Top View)
A1 A2
NC NC
A9 A10
NC NC
B1 B9 B10
NC NC NC
C3
WP#
C4
ALE
C5
VSS
C6
CE#
C7
WE#
C8
RB#
D3 D4 D5 D6 D7 D8
VCC
RE#
CLE
NC
NC
NC
E3 E4 E5 E6 E7 E8
NC NC NC NC NC NC
F3 F4 F5 F6 F7 F8
NC NC NC NC VSS NC
G3 G4 G5 G6 G7 G8
NC
VCC
NC
I/O13
I/O15
NC
H3 H4 H5 H6 H7 H8
I/O8
I/O0
I/O10
I/O12
I/O14
Vcc
J3 J4 J5 J6 J7 J8
I/O9 I/O1 I/O11 VCC I/O5 I/O7
K3 K4 K5 K6 K7 K8
VSS I/O2 I/O3 I/O4 I/O6 VSS
L1 L2
NC NC
L9 L10
NC NC
M1 M2
NC NC
M9 M10
NC NC
1.3 Pin Description
Table 1.2 Pin Description
Pin Name
Description
I/O0 - I/O7 (×8) Inputs/Outputs. The I/O pins are used for command input, address input, data input, and data output. The
I/O8 - I/O15 (×16) I/O pins float to High-Z when the device is deselected or the outputs are disabled.
CLE
Command Latch Enable. This input activates the latching of the I/O inputs inside the Command Register on the rising
edge of Write Enable (WE#).
ALE
Address Latch Enable. This input activates the latching of the I/O inputs inside the Address Register on the rising
edge of Write Enable (WE#).
CE# Chip Enable. This input controls the selection of the device. When the device is not busy CE# low selects the memory.
WE#
Write Enable. This input latches Command, Address and Data. The I/O inputs are latched on the rising edge of WE#.
RE#
WP#
Read Enable. The RE# input is the serial data-out control, and when active drives the data onto the I/O bus. Data is
valid tREA after the falling edge of RE# which also increments the internal column address counter by one.
Write Protect. The WP# pin, when low, provides hardware protection against undesired data modification
(program / erase).
R/B#
Ready Busy. The Ready/Busy output is an Open Drain pin that signals the state of the memory.
VCC
VSS
Supply Voltage. The VCC supplies the power for all the operations (Read, Program, Erase). An internal lock circuit
prevents the insertion of Commands when VCC is less than VLKO.
Ground.
NC Not Connected.
Notes:
1. A 0.1 µF capacitor should be connected between the VCC Supply Voltage pin and the VSS Ground pin to decouple the current surges from the power supply. The PCB
track widths must be sufficient to carry the currents required during program and erase operations.
2. An internal voltage detector disables all functions whenever VCC is below 1.8V to protect the device from any involuntary program/erase during power transitions.
Document Number: 002-00676 Rev. *S
Page 6 of 73

6 Page



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部品番号部品説明メーカ
S34ML01G1

3V SLC NAND Flash

Cypress Semiconductor
Cypress Semiconductor
S34ML01G1

(S34ML01G1 - S34ML04G1) SLC NAND Flash Memory

Spansion
Spansion
S34ML01G2

NAND Flash Memory

Cypress Semiconductor
Cypress Semiconductor


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