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PDF NJG1697EM1 Data sheet ( Hoja de datos )
| Número de pieza | NJG1697EM1 | |
| Descripción | High Isolation SPDT SWITCH | |
| Fabricantes | New Japan Radio | |
| Logotipo |  |
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NJG1697EM1
High Isolation SPDT SWITCH
I GENERAL DESCRIPTION
The NJG1697EM1 is a 1bit control GaAs high isolation SPDT switch
MMIC. The NJG1697EM1 features very high isolation and low control
voltage. It has integrated DC blocking capacitor at PC port.
It has integrated ESD protection circuits the IC to achieve high ESD
tolerance.
The small and thin 6-pin DFN6-M1 package is adopted.
I PACKAGE OUTLINE
NJG1697EM1
I APPLICATIONS
Multi-mode 2G/3G and LTE application receive system
Pre PA switching, reception bands switching applications
General purpose switching applications
I FEATURES
G Low voltage logic control
VCTL(H)=1.8V typ.
G Low voltage operation
VDD=2.7V typ.
G High isolation
50dB typ. @f=1.0GHz, PIN=0dBm
48dB typ. @f=2.0GHz, PIN=0dBm
43dB typ. @f=2.7GHz, PIN=0dBm
G Low insertion loss
0.45dB typ. @f=1.0GHz, PIN=0dBm
0.50dB typ. @f=2.0GHz, PIN=0dBm
0.55dB typ. @f=2.7GHz, PIN=0dBm
G Ultra small & ultra thin package
DFN6-M1 Package (Package size: 1.0 x 1.0 x 0.38mm)
G RoHS compliant and Halogen Free, MSL1
I PIN CONFIGURATION
(TOP VIEW)
GND
3
P2 4
2 P1
I TRUTH TABLE
VCTL 5
6
PC
“H”=VCTL(H), “L”=VCTL(L)
ON PATH
PC-P1
PC-P2
1 VDD
VCTL
H
L
Pin connection
1. VDD
2. P1
3. GND
4. P2
5. VCTL
6. PC
NOTE: Please note that any information on this datasheet will be subject to change.
Ver.2014-9-1
-1-
1 page  
I ELECTRICAL CHARACTERISTICS (With Application circuit)
NJG1697EM1
-5-
5 Page 
I APPLIED CIRCUIT BOARD EXAMPLES
(TOP VIEW)
C2 C1
P2
C4 C3
VCTL
VDD
PC
<PCB LAYOUT GUIDELINE>
(TOP VIEW)
NJG1697EM1
PCB:
FR-4, t=0.2mm
Capacitor Size: 1005 (1.0 x 0.5 mm)
Strip Line Width: 0.4mm
PCB Size:
19.4 x 15.0mm
Through Hole Diameter: 0.2mm
P1 Losses of PCB, capacitors and connectors
Paths
Frequency
(GHz)
0.5
Loss
(dB)
0.12
PC-P1,
PC-P2
1.0
2.0
0.17
0.30
2.7 0.36
PCB
PKG Terminal
PKG Outline
GND Via Hole
Diameter: φ= 0.2mm
To achieve the isolation specified in the datasheet, it is needed that the ground plane located beneath
the device as shown above figure. In this case, the minimum line and space width of PCB is 0.1mm.
PRECAUTIONS
[1] The DC current at RF ports must be equal to zero, which can be achieved with DC blocking capacitors (C1,
C2). (However, in case there is no possibility that DC current flows, the DC blocking capacitors are unnecessary,
i.e. the RF signals are fed by SAW filters that block DC current by nature, etc.)
[2] To reduce stripline influence on RF characteristics, please locate the bypass capacitor C3 and C4 close to
VDD and VCTL terminal.
[3] For good isolation, the GND terminals must be connected to the PCB ground plane of substrate, and the
through-holes connecting the backside ground plane should be placed near by the pin connection.
- 11 -
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet NJG1697EM1.PDF ] | |
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