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PDF NJG1683ME7 Data sheet ( Hoja de datos )
| Número de pieza | NJG1683ME7 | |
| Descripción | High Isolation X-SP3T (DP6T) SWITCH | |
| Fabricantes | New Japan Radio | |
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Hay una vista previa y un enlace de descarga de NJG1683ME7 (archivo pdf) en la parte inferior de esta página. Total 13 Páginas | ||
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NJG1683ME7
High Isolation X-SP3T (DP6T) SWITCH
I GENERAL DESCRIPTION
The NJG1683ME7 is a GaAs X (cross) - SP3T (DP6T) switch
MMIC for switching of balanced (differential) triple band filters,
upper pin compatible for NJG1655ME7. It features low insertion
loss and very high isolation for balanced signal input which makes
it much suited for balanced filter switching.
The ESD protection circuits are integrated in the IC to achieve
high ESD tolerance.
The ultra-small and ultra-thin EQFN18-E7 package is adopted.
I PACKAGE OUTLINE
NJG1683ME7
*) The X-SP3T is a paired SP3T switch that features two identical SP3T switches being integrated into one chip. The two
SP3T switches are controlled synchronously, and their respective RF lines cross each other on the chip.
I APPLICATIONS
Switching of balanced type filters (Triple band) application
Suitable for 3G and LTE application
I FEATURES
G Low operation voltage
G Low control voltage
G High isolation
(Balanced mode)
G Low insertion loss
G Small package
VDD=1.5~4.5V
VCTL(H)=1.8V typ.
55dB typ. @f=1.0GHz, PIN=0dBm
47dB typ. @f=2.0GHz, PIN=0dBm
45dB typ. @f=2.7GHz, PIN=0dBm
0.35dB typ. @f=1.0GHz, PIN=0dBm
0.45dB typ. @f=2.0GHz, PIN=0dBm
0.60dB typ. @f=2.7GHz, PIN=0dBm
EQFN18-E7 (Package size: 2.0mm x 2.0mm x 0.397mm typ.)
G RoHS compliant and Halogen Free
G MSL1
I PIN CONFIGURATION (Top View)
18 17 16 15
1 14
2
D EC OD ER
13
3 12
4 11
5 10
6789
Pin connection
1. GND
10. GND
2. NC(GND) 11. PCB
3. P2A
12. PCA
4. P2B
13. VDD
5. GND
14. GND
6. P1B
15. VCTL2
7. P1A
16. VCTL1
8. GND
17. P3B
9. NC(GND) 18. P3A
I TRUTH TABLE
ON PATH
“H”=VCTL(H), “L”=VCTL(L)
VCTL1 VCTL2
PCA-P1A PCB-P1B H L
PCA-P2A PCB-P2B L L
PCA-P3A PCB-P3B L H
NOTE: The information on this datasheet is subject to change without notice.
Ver.2013-04-09
-1-
1 page  
NJG1683ME7
I ELECTRICAL CHARACTERISTICS (With Application circuit, Loss of external circuit are excluded)
Insertion Loss vs. Frequency
( PC-P1 ON, V =2.7V, V =1.8V, V =0V )
DD CTL1 CTL2
0.0
PCA-P1A
PCB-P1B
-0.5
-1.0
-1.5
-2.0
0.5
1.0 1.5 2.0 2.5
Frequency (GHz)
3.0
Insertion Loss vs. Frequency
( PC-P2 ON, V =2.7V, V =0V, V =0V )
0.0
DD
CTL1
CTL2
PCA-P2A
PCB-P2B
-0.5
-1.0
-1.5
-2.0
0.5
1.0 1.5 2.0 2.5
Frequency (GHz)
3.0
Insertion Loss vs. Frequency
( PC-P3 ON, V =2.7V, V =0V, V =1.8V )
0.0
DD
CTL1
CTL2
PCA-P3A
PCB-P3B
-0.5
-1.0
-1.5
-2.0
0.5
1.0 1.5 2.0 2.5
Frequency (GHz)
3.0
VSWR vs. Frequency
( PC-P1 ON, V =2.7V, V =1.8V, V =0V )
DD CTL1 CTL2
3.0
PCA
PCB
P1A
2.5 P1B
2.0
1.5
1.0
0.5
1.0 1.5 2.0 2.5
Frequency (GHz)
3.0
VSWR vs. Frequency
( PC-P2 ON, V =2.7V, V =0V, V =0V )
DD
CTL1
CTL2
3.0
PCA
PCB
P2A
2.5 P2B
2.0
1.5
1.0
0.5
1.0 1.5 2.0 2.5
Frequency (GHz)
3.0
VSWR vs. Frequency
( PC-P3 ON, V =2.7V, V =0V, V =1.8V )
DD
CTL1
CTL2
3.0
PCA
PCB
P3A
2.5 P3B
2.0
1.5
1.0
0.5
1.0 1.5 2.0 2.5
Frequency (GHz)
3.0
-5-
5 Page 
I TEST PCB LAYOUT
(TOP VIEW)
P3A P3B
P2A
P2B
C8
C1
C2
C3
VCTL1
C7 VCTL2
VDD
C9
C6
C5
C4
NJG1683ME7
PCA
PCB:
FR-4, t=0.2mm
Capacitor Size: 1005
Strip Line Width: 0.4mm
PCB Size:
26 x 26mm
Losses of PCB, capacitors and connectors
PCB
Frequency (GHz)
1.0
2.0
2.7
Loss (dB)
0.33
0.57
0.71
P1B
<PCB LAYOUT GUIDELINE>
P1A
14 13 12 11 10
15 9
16 8
17 7
18 6
1 234 5
PCB Pattern
Through-hole (radius: 0.10mm)
Pin
Note2:
The ground plane and the through-holes under Tab, as shown
in the picture, are not necessities. There is no problem in deleting
them in the practical PCB design, though in such case beware
that the GND terminals (pin 1, 2, 8, 9 and 10 as for this particular
design shown in the picture) still need through-holes being
located in their vicinities.
PRECAUTIONS
[1] The DC current at RF ports must be equal to zero, which can be achieved with DC blocking capacitors
(C1~C8).
(However, in case there is no possibility that DC current flows, the DC blocking capacitors are unnecessary, e.g.
the RF signals are fed by SAW filters that block DC current by nature, etc.)
[2] To reduce stripline influence on RF characteristics, please locate the bypass capacitor (C9) close to VDD
terminal.
[3] For good isolation, the GND terminals must be connected to the PCB ground plane of substrate, and the
through-holes connecting the backside ground plane should be placed near by the pin connection.
- 11 -
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet NJG1683ME7.PDF ] | |
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