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PDF ADM1169 Data sheet ( Hoja de datos )
| Número de pieza | ADM1169 | |
| Descripción | Super Sequencer | |
| Fabricantes | Analog Devices | |
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Data Sheet
Super Sequencer with Margining Control
and Nonvolatile Fault Recording
ADM1169
FEATURES
Complete supervisory and sequencing solution for up to
8 supplies
16-event deep black box nonvolatile fault recording
8 supply fault detectors enable supervision of supplies to
<0.5% accuracy at all voltages at 25°C
<1.0% accuracy across all voltages and temperatures
4 selectable input attenuators allow supervision of supplies to
14.4 V on VH and 6 V on VP1 to VP3 (VPx)
4 dual-function inputs, VX1 to VX4 (VXx)
High impedance input to supply fault detector with
thresholds between 0.573 V and 1.375 V
General-purpose logic input
8 programmable driver outputs, PDO1 to PDO8 (PDOx)
Open-collector with external pull-up
Push/pull output, driven to VDDCAP or VPx
Open-collector with weak pull-up to VDDCAP or VPx
Internally charge-pumped high drive for use with external
NFET (PDO1 to PDO6 only)
SE implements state machine control of PDO outputs
State changes conditional on input events
Enables complex control of boards
Power-up and power-down sequence control
Fault event handling
Interrupt generation on warnings
Watchdog function can be integrated in SE
Program software control of sequencing through SMBus
Complete voltage margining solution for 4 voltage rails
4 voltage output 8-bit DACs (0.300 V to 1.551 V) allow voltage
adjustment via dc-to-dc converter trim/feedback node
12-bit ADC for readback of all supervised voltages
Reference input (REFIN) has 2 input options
Driven directly from 2.048 V (±0.25%) REFOUT pin
More accurate external reference for improved ADC
performance
Device powered by the highest of VPx, VH for improved
redundancy
User EEPROM: 256 bytes
Industry-standard 2-wire bus interface (SMBus)
Guaranteed PDO low with VH, VPx = 1.2 V
Available in 32-lead LQFP and 40-lead LFCSP packages
APPLICATIONS
Central office systems
Servers/routers
Multivoltage system line cards
DSP/FPGA supply sequencing
In-circuit testing of margined supplies
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
VX1
VX2
VX3
VX4
VP1
VP2
VP3
VH
AGND
FUNCTIONAL BLOCK DIAGRAM
REFIN REFOUT REFGND SDA SCL A1 A0
ADM1169
VREF
SMBus
INTERFACE
12-BIT
SAR ADC
CLOSED-LOOP
MARGINING SYSTEM
DUAL-
FUNCTION
INPUTS
(LOGIC INPUTS
OR
SFDs)
PROGRAMMABLE
RESET
GENERATORS
(SFDs)
FAULT
RECORDING
EEPROM
SEQUENCING
ENGINE
CONFIGURABLE
OUTPUT
DRIVERS
(HV CAPABLE OF
DRIVING GATES
OF NFET)
CONFIGURABLE
OUTPUT
DRIVERS
(LV CAPABLE
OF DRIVING
LOGIC SIGNALS)
PDO1
PDO2
PDO3
PDO4
PDO5
PDO6
PDO7
PDO8
VOUT VOUT VOUT VOUT
DAC DAC DAC DAC
VDD
ARBITRATOR
PDOGND
VDDCAP
DAC1 DAC2 DAC3 DAC4
VCCP
Figure 1.
GENERAL DESCRIPTION
GND
The ADM1169 Super Sequencer® is a configurable supervisory/
sequencing device that offers a single-chip solution for supply
monitoring and sequencing in multiple supply systems. In addition
to these functions, the ADM1169 integrates a 12-bit ADC and
four 8-bit voltage output DACs. These circuits can be used to
implement a closed-loop margining system that enables supply
adjustment by altering either the feedback node or reference of
a dc-to-dc converter using the DAC outputs.
Supply margining can be performed with a minimum of external
components. The margining loop can be used for in-circuit
testing of a board during production (for example, to verify
board functionality at −5% of nominal supplies), or it can be
used dynamically to accurately control the output voltage of
a dc-to-dc converter.
For more information about the ADM1169 register map, refer
to the AN-721 Application Note.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2011–2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
ADM1169
Data Sheet
SPECIFICATIONS
VH = 3.0 V to 14.4 V,1 VPx = 3.0 V to 6.0 V,1 TA = −40°C to +85°C, unless otherwise noted.
Table 1.
Parameter
POWER SUPPLY ARBITRATION
VH, VPx
VPx
VH
VDDCAP
CVDDCAP
POWER SUPPLY
Supply Current, IVH, IVPx
Additional Currents
All PDOx FET Drivers On
Current Available from VDDCAP
DAC Supply Currents
ADC Supply Current
EEPROM Erase Current
SUPPLY FAULT DETECTORS
VH Pin
Input Impedance
Input Attenuator Error
Detection Ranges
High Range
Midrange
VPx Pins
Input Impedance
Input Attenuator Error
Detection Ranges
Midrange
Low Range
Ultralow Range
VXx Pins
Input Impedance
Ultralow Range
Absolute Accuracy
Threshold Resolution
Digital Glitch Filter
Min Typ Max Unit Test Conditions/Comments
3.0 V Minimum supply required on one of VH, VPx
6.0 V
Maximum VDDCAP = 5.1 V, typical
14.4 V
VDDCAP = 4.75 V
2.7
4.75 5.4 V
Regulated LDO output
10 μF Minimum recommended decoupling
capacitance
4.2 6
mA VDDCAP = 4.75 V, PDO1 to PDO8 off, DACs off,
ADC off
1
2
2.2
1
10
mA VDDCAP = 4.75 V, PDO1 to PDO6 loaded with
1 μA each, PDO7 to PDO8 off
mA Maximum additional load that can be drawn
from all PDO pull-ups to VDDCAP
mA Four DACs on with 100 μA maximum load on each
mA Running round-robin loop
mA 1 ms duration only, VDDCAP = 3 V
6
2.5
2.5
1.25
0.573
1
0.573
52
±0.05
kΩ
%
14.4 V
6V
52
±0.05
kΩ
%
6
3
1.375
V
V
V
1.375
±1
MΩ
V
%
8 Bits
0 μs
100 μs
Midrange and high range
Low range and midrange
No input attenuation error
No input attenuation error
Internal reference VREF error + DAC nonlinearity +
comparator offset error
Minimum programmable filter length
Maximum programmable filter length
Rev. B | Page 4 of 33
5 Page 
ADM1169
TYPICAL PERFORMANCE CHARACTERISTICS
6
5
4
3
2
1
0
0123456
VVP1 (V)
Figure 5. VVDDCAP vs. VVP1
6
5
4
3
2
1
0
0
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0
2 4 6 8 10 12 14 16
VVH (V)
Figure 6. VVDDCAP vs. VVH
1234
VVP1 (V)
Figure 7. IVP1 vs. VVP1 (VP1 as Supply)
5
6
Data Sheet
180
160
140
120
100
80
60
40
20
0
0
12345
VVP1 (V)
Figure 8. IVP1 vs. VVP1 (VP1 Not as Supply)
6
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0
2 4 6 8 10 12 14 16
VVH (V)
Figure 9. IVH vs. VVH (VH as Supply)
350
300
250
200
150
100
50
0
0
12345
VVH (V)
Figure 10. IVH vs. VVH (VH Not as Supply)
6
Rev. B | Page 10 of 33
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ADM1169.PDF ] | |
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