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VSC8117 の電気的特性と機能

VSC8117のメーカーはVitesse Semiconductorです、この部品の機能は「ATM/SONET/SDH 622/155 Mb/s Transceiver Mux/Demux」です。


製品の詳細 ( Datasheet PDF )

部品番号 VSC8117
部品説明 ATM/SONET/SDH 622/155 Mb/s Transceiver Mux/Demux
メーカ Vitesse Semiconductor
ロゴ Vitesse Semiconductor ロゴ 




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VSC8117 Datasheet, VSC8117 PDF,ピン配置, 機能
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC8117
ATM/SONET/SDH 622/155 Mb/s Transceiver Mux/Demux
with Integrated Clock Generation and Clock Recovery
Features
Operates at Either STS-3/STM-1 (155.52Mb/s)
or STS-12/STM-4 (622.08Mb/s) Data Rates
• Compatible with Industry ATM UNI Devices
• On Chip Clock Generation of the 155.52MHz
or 622.08MHz High Speed Clock (Mux)
• On Chip Clock Recovery of the 155.52MHz or
622.08MHz High Speed Clock (Demux)
• 8 Bit Parallel TTL Interface
• SONET/SDH Frame Recovery
• Loss of Signal (LOS) Input & LOS Detection
• +3.3V/5V programmable PECL Serial Interface
• Provides Equipment, Facilities and Split Loop-
back Modes as well as Loop Timing Mode
• Provides TTL and PECL reference clock inputs
• Meets Bellcore, ITU and ANSI Specifications for
Jitter Performance
• Low Power - 1.0 Watts Typical
• 64 PQFP Package
General Description
The VSC8117 is an ATM/SONET/SDH compatible transceiver integrating an on-chip Clock Multiplication
Unit (PLL) for the high speed clock as well as a clock and data recovery unit (CRU) with 8 bit serial-to-parallel
and parallel-to-serial data conversion. The PLL clock is used for serialization in the transmit direction (Mux).
The recovered clock is used for deserialization in the receive direction (Demux). The demultiplexer contains
SONET/SDH frame detection and recovery. The device provides facility loopback, equipment loopback, and
loop timing modes. The part is packaged in a 64-pin PQFP with integrated heat spreader for optimum thermal
performance and reduced cost. The VSC8117 provides an integrated solution for ATM physical layers and
SONET/SDH systems applications.
Functional Description
The VSC8117 is designed to provide a SONET/SDH compliant interface between the high speed optical
networks and the lower speed User Network Interface devices such as the PM5355 S/UNI-622. The VSC8117
converts 8 bit parallel data at 77.76Mb/s or 19.44Mb/s to a serial bit stream at 622.08Mb/s or 155.52Mb/s
respectively. The device also provides a Facility Loopback function which loops the received high speed data
and clock (optionally recovered on-chip) directly to the high speed transmit outputs. A Clock Multiplier Unit
(CMU) is integrated into the transmit circuit to generate the high speed clock for the serial output data stream
from input reference frequencies of 19.44 or 77.76 MHz. The CMU can be bypassed with the recovered clock in
loop timing mode thus synchronizing the entire part to a single clock. The block diagram on page 2 shows the
major functional blocks associated with the VSC8117.
The receive section provides the serial-to-parallel conversion, converting the 155.52Mb/s or 622.08Mb/s bit
stream to an 8 bit parallel output at 19.44Mb/s or 77.76Mb/s respectively. A Clock Recovery Unit (CRU) is inte-
grated into the receive circuit to recover the high speed clock from the received serial data stream. The receive
section provides an Equipment Loopback function which will loop the low speed transmit data and clock back
through the receive section to the 8 bit parallel data bus and clock outputs. The VSC8117 also provides the
option of selecting between either its internal CRU’s recovered clock and data signals or optics containing a
G52221-0, Rev. 4.1
1/8/00
© VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 1

1 Page





VSC8117 pdf, ピン配列
Data Sheet
VSC8117
VITESSE
SEMICONDUCTOR CORPORATION
ATM/SONET/SDH 622/155 Mb/s Transceiver Mux/Demux
with Integrated Clock Generation and Clock Recovery
Transmit Section
Byte-wide data is presented to TXIN[7:0] and is clocked into the part on the rising edge of TXLSCKOUT.
TXLSCKOUT also latches TXIN[7:0] into the part as shown in Figure 1. The data is then serialized (MSB lead-
ing) and presented at the TXDATAOUT+/- pins. The serial output stream is synchronized to the CMU generated
clock which is a phase locked and frequency scaled version of the input reference clock. External control inputs
CMUFREQSEL and STS-12 select the multiply ratio of the CMU for either STS-3 (155MbS) or STS-12
(622Mb/s) transmission (see Table 10). A divide-by-8 version of the CMU clock (TXLSCKOUT) should be
used to synchronize the transmit interface of the UNI device to the transmit input registers on the VSC8117.
Figure 1: Data and Clock Transmit Block Diagram
TXDATAOUT+
TXDATAOUT-
VSC8117
QD
QD
TXIN[7:0]
TXLSCKIN
PM5355
QD
REFCLK
CMU
Divide-by-8
TXLSCKOUT
Receive Section
High speed Non-Return to Zero (NRZ) serial data at 155Mb/s or 622Mb/s are received by the RXDATAIN
inputs. The CRU recovers the high speed clock from the serial data input. The serial data is converted to byte-
wide parallel data and presented on RXOUT[7:0] pins. A divide-by-8 version of the high-speed clock
(RXLSCKOUT) should be used to synchronize the byte-serial RXOUT[7:0] data with the receive portion of the
UNI device. The on-chip CRU is by-passed by setting the DSBLCRU input high. In this mode, the serial input
data and corresponding clock are received by the RXDATAIN and RXCLKIN inputs respectively. RXDATAIN
is clocked in on the rising edge of RXCLKIN+. See Figure 2.
The receive section also includes frame detection and recovery circuitry which detects the SONET/SDH
frame, aligns the received serial data on byte boundaries, and initiates a frame pulse on FP coincident with the
byte aligned data. The frame recovery is initiated when OOF is held high which must occur at least 4 byte clock
cycles before the A1A2 boundary. The OOF input control is a level-sensitive signal, and the VSC8117 will con-
tinually perform frame detection and recovery as long as this pin is held high even if 1 or more frames has been
detected. Frame detection and recovery occurs when a series of three A1 bytes followed by three A2 bytes has
been detected. The parallel output data on RXOUT[7:0] will be byte aligned starting on the third A2 byte. When
a frame is detected, a single byte clock period long pulse is generated on FP which is synchronized with the
byte-aligned third A2 byte on RXOUT[7:0]. The frame detector sends a FP pulse only if OOF is high.
G52221-0, Rev. 4.1
1/8/00
© VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 3


3Pages


VSC8117 電子部品, 半導体
VITESSE
SEMICONDUCTOR CORPORATION
ATM/SONET/SDH 622/155 Mb/s Transceiver Mux/Demux
with Integrated Clock Generation and Clock Recovery
Data Sheet
VSC8117
Split Loopback
Equipment and facility loopback modes can be enabled simultaneously. In this case, high-speed serial data
received (RXDATAIN) is mux’d through to the high-speed serial output (TXDATAOUT). The low-speed trans-
mit byte wide bus(TXIN[7:0]) and (TXLSCKIN) are mux’d into the low-speed byte wide receive output bus
(RXOUT[7:0]) and (RXLSCKOUT). See Figure 5.
Figure 5: Split Loopback Datapath
RXDATAIN
RXCLKIN
DSBLCRU
TXDATAOUT
CRU
DQ
Recovered
Clock
0
1
QD
1:8
Serial to
Parallel
8:1
Parallel to
Serial
PLL ÷8
DQ
QD
TXLSCKIN
RXOUT[7:0]
RXLSCKOUT
TXIN[7:0]
Loop Timing
LOOPTIM0 mode bypasses the CMU when the LOOPTIM0 input is asserted high. In this mode the CMU
is bypassed by using the receive clock (RXCLKIN), and the entire part is synchronously clocked from a single
external source.
Clock Synthesis
The VSC8117 uses an integrated phase-locked loop (PLL) for clock synthesis of the 622MHz high speed
clock used for serialization in the transmitter section. The PLL is comprised of a phase-frequency detector
(PFD), an integrating operation amplifier and a voltage controlled oscillator (VCO) configured in classic feed-
back system. The PFD compares the selected divided down version of the 622MHz VCO (pin CMUFREQSEL
selects the divide-by ratios of 8 or 32, see Table 10) and the reference clock. The integrator provides a transfer
function between input phase error and output voltage control. The VCO portion of the PLL is a voltage con-
trolled ring-oscillator with a center frequency of 622MHz.
The reactive elements of the integrator are located off-chip and are connected to the feedback loop of the
amplifier through the CP1, CP2, CN1 and CN2 pins. The configuration of these external surface mounted
capacitors is shown in Figure 6. Table 1 shows the recommended external capacitor values for the configurable
reference frequencies.
Page 6
© VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
G52221-0, Rev 4.1
1/8/00

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