S29PL-J Datasheet PDF - Cypress Semiconductor
| Part Number | S29PL-J | |
| Description | Page Mode and Simultaneous Read/Write Flash memory device | |
| Manufacturers | Cypress Semiconductor | |
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S29PL-J
128-/128-/64-/32-Mbit (8/8/4/2M x 16-Bit)
3V, Flash with Enhanced VersatileIO™
Distinctive Characteristics
Architectural Advantages
128-/128-/64-/32-Mbit Page Mode devices
– Page size of 8 words: Fast page read access from random
locations within the page
Single power supply operation
– Full Voltage range: 2.7 to 3.6 V read, erase, and program
operations for battery-powered applications
Dual Chip Enable inputs (only in PL129J)
– Two CE# inputs control selection of each half of the
memory space
Simultaneous Read/Write Operation
– Data can be continuously read from one bank while
executing erase/program functions in another bank
– Zero latency switching from write to read operations
FlexBank Architecture (PL127J/PL064J/PL032J)
– 4 separate banks, with up to two simultaneous operations
per device
– Bank A:
PL127J -16 Mbit (4 Kw 8 and 32 Kw 31)
PL064J - 8 Mbit (4 Kw 8 and 32 Kw 15)
PL032J - 4 Mbit (4 Kw 8 and 32 Kw 7)
– Bank B:
PL127J - 48 Mbit (32 Kw 96)
PL064J - 24 Mbit (32 Kw 48)
PL032J - 12 Mbit (32 Kw 24)
– Bank C:
PL127J - 48 Mbit (32 Kw 96)
PL064J - 24 Mbit (32 Kw 48)
PL032J - 12 Mbit (32 Kw 24)
– Bank D:
PL127J -16 Mbit (4 Kw 8 and 32 Kw 31)
PL064J - 8 Mbit (4 Kw 8 and 32 Kw 15)
PL032J - 4 Mbit (4 Kw 8 and 32 Kw 7)
FlexBank Architecture (PL129J)
– 4 separate banks, with up to two simultaneous operations
per device
– CE#1 controlled banks:
Bank 1A: PL129J - 16-Mbit (4Kw 8 and 32Kw 31)
Bank 1B: PL129J - 48-Mbit (32Kw 96)
– CE#2 controlled banks:
Bank 2A: PL129J - 48-Mbit (32 Kw 96)
Bank 2B: PL129J - 16-Mbit (4 Kw 8 and 32 Kw 31)
Enhanced VersatileI/O (VIO) Control
– Output voltage generated and input voltages tolerated on
all control inputs and I/Os is determined by the voltage on
the VIO pin
– VIO options at 1.8 V and 3 V I/O for PL127J and PL129J
devices
– 3V VIO for PL064J and PL032J devices
Secured Silicon Sector region
– Up to 128 words accessible through a command sequence
– Up to 64 factory-locked words
– Up to 64 customer-lockable words
Both top and bottom boot blocks in one device
Manufactured on 110-nm process technology
Data Retention: 20 years typical
Cycling Endurance: 1 million cycles per sector typical
Performance Characteristics
High Performance
– Page access times as fast as 20 ns
– Random access times as fast as 55 ns
Power consumption (typical values at 10 MHz)
– 45 mA active read current
– 17 mA program/erase current
– 0.2 A typical standby mode current
Software Features
Software command-set compatible with JEDEC 42.4
standard
– Backward compatible with Am29F, Am29LV, Am29DL, and
AM29PDL families and MBM29QM/RM, MBM29LV,
MBM29DL, MBM29PDL families
CFI (Common Flash Interface) compliant
– Provides device-specific information to the system,
allowing host software to easily reconfigure for different
Flash devices
Erase Suspend / Erase Resume
– Suspends an erase operation to allow read or program
operations in other sectors of same bank
Program Suspend / Program Resume
– Suspends a program operation to allow read operation
from sectors other than the one being programmed
Unlock Bypass Program command
Reduces overall programming time when issuing multiple
program command sequences
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 002-00615 Rev. *B
• San Jose, CA 95134-1709 • 408-943-2600
Revised August 10, 2016
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S29PL-J
2.1 Page Mode Features
The page size is 8 words. After initial page access is accomplished, the page mode operation provides fast read access speed of
random locations within that page.
2.2 Standard Flash Memory Features
The device requires a single 3.0 volt power supply (2.7 V to 3.6 V) for both read and write functions. Internally generated and
regulated voltages are provided for the program and erase operations.
The device is entirely command set compatible with the JEDEC 42.4 single-power-supply Flash standard. Commands are written
to the command register using standard microprocessor write timing. Register contents serve as inputs to an internal state-machine
that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming
and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices.
Device programming occurs by executing the program command sequence. The Unlock Bypass mode facilitates faster
programming times by requiring only two write cycles to program data instead of four. Device erasure occurs by executing the erase
command sequence.
The host system can detect whether a program or erase operation is complete by reading the DQ7 (Data# Polling) and DQ6 (toggle)
status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command.
The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other
sectors. The device is fully erased when shipped from the factory.
Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power
transitions. The hardware sector protection feature disables both program and erase operations in any combination of sectors of
memory. This can be achieved in-system or via programming equipment.
The Erase Suspend/Erase Resume feature enables the user to put erase on hold for any period of time to read data from, or
program data to, any sector that is not selected for erasure. True background erase can thus be achieved. If a read is needed from
the Secured Silicon Sector area (One Time Program area) after an erase suspend, then the user must use the proper command
sequence to enter and exit this region.
The Program Suspend/Program Resume feature enables the user to hold the program operation to read data from any sector that
is not selected for programming. If a read is needed from the Secured Silicon Sector area, Persistent Protection area, Dynamic
Protection area, or the CFI area, after a program suspend, then the user must use the proper command sequence to enter and exit
this region.
The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters
the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in
both these modes. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The data is
programmed using hot electron injection.
Document Number: 002-00615 Rev. *B
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Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for S29PL-J electronic component. |
| Information | Total 30 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ S29PL-J.PDF Datasheet ] | |
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