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S25FL512S の電気的特性と機能

S25FL512SのメーカーはCypress Semiconductorです、この部品の機能は「512 Mbit (64 Mbyte) 3.0V SPI Flash Memory」です。


製品の詳細 ( Datasheet PDF )

部品番号 S25FL512S
部品説明 512 Mbit (64 Mbyte) 3.0V SPI Flash Memory
メーカ Cypress Semiconductor
ロゴ Cypress Semiconductor ロゴ 




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S25FL512S Datasheet, S25FL512S PDF,ピン配置, 機能
S25FL512S
512 Mbit (64 Mbyte)
3.0V SPI Flash Memory
Features
CMOS 3.0 Volt Core with Versatile I/O
Serial Peripheral Interface with Multi-I/O
Density
– 512 Mbits (64 Mbytes)
Serial Peripheral Interface (SPI)
– SPI Clock polarity and phase modes 0 and 3
– Double Data Rate (DDR) option
– Extended Addressing: 32-bit address
– Serial Command set and footprint compatible with S25FL-A,
S25FL-K, and S25FL-P SPI families
– Multi I/O Command set and footprint compatible with
S25FL-P SPI family
READ Commands
– Normal, Fast, Dual, Quad, Fast DDR, Dual DDR, Quad DDR
– AutoBoot - power up or reset and execute a Normal or Quad read
command automatically at a preselected address
– Common Flash Interface (CFI) data for configuration information.
Programming (1.5 Mbytes/s)
– 512-byte Page Programming buffer
– Quad-Input Page Programming (QPP) for slow clock systems
– Automatic ECC -internal hardware Error Correction Code
generation with single bit error correction
Erase (0.5 to 0.65 Mbytes/s)
– Uniform 256-kbyte sectors
Cycling Endurance
– 100,000 Program-Erase Cycles
Data Retention
– 20 Year Data Retention
Security features
– One Time Program (OTP) array of 1024 bytes
– Block Protection:
– Status Register bits to control protection against program or erase
of a contiguous range of sectors.
– Hardware and software control options
– Advanced Sector Protection (ASP)
– Individual sector protection controlled by boot code or password
Cypress® 65 nm MirrorBit® Technology with EclipseArchitecture
Core Supply Voltage: 2.7V to 3.6V
I/O Supply Voltage: 1.65V to 3.6V
– SO16 and FBGA packages
Temperature Range:
– Industrial (-40°C to +85°C)
– Industrial Plus (-40°C to +105°C)
– Extended (-40°C to +125°C)
– Automotive, AEC-Q100 Grade 3 (–40°C to +85°C)
– Automotive, AEC-Q100 Grade 2 (–40°C to +105°C)
– Automotive, AEC-Q100 Grade 1 (–40°C to +125°C)
Packages (all Pb-free)
– 16-lead SOIC (300 mil)
– BGA-24 6 x 8 mm
– 5 x 5 ball (FAB024) and 4 x 6 ball (FAC024) footprint options
– Known Good Die and Known Tested Die
Logic Block Diagram
CS#
SCK
SI/IO0
SO/IO1
WP#/IO2
HOLD#/IO3
RESET#
I/O
SRAM
Control
Logic
MirrorBit Array
Y Decoders
Data Latch
Data Path
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-98284 Rev. *J
• San Jose, CA 95134-1709 • 408-943-2600
Revised September 20, 2016

1 Page





S25FL512S pdf, ピン配列
S25FL512S
Contents
Features................................................................................. 1
Logic Block Diagram............................................................ 1
Performance Summary ........................................................ 2
1. Overview ....................................................................... 4
1.1 General Description ....................................................... 4
1.2 Migration Notes.............................................................. 5
1.3 Glossary......................................................................... 7
1.4 Other Resources............................................................ 7
Hardware Interface
2. Signal Descriptions ..................................................... 8
2.1 Input/Output Summary................................................... 8
2.2 Address and Data Configuration.................................... 9
2.3 RESET# ......................................................................... 9
2.4 Serial Clock (SCK) ......................................................... 9
2.5 Chip Select (CS#) .......................................................... 9
2.6 Serial Input (SI) / IO0 ................................................... 10
2.7 Serial Output (SO) / IO1............................................... 10
2.8 Write Protect (WP#) / IO2 ............................................ 10
2.9 Hold (HOLD#) / IO3 ..................................................... 10
2.10 Core Voltage Supply (VCC) .......................................... 11
2.11 Versatile I/O Power Supply (VIO) ................................. 11
2.12 Supply and Signal Ground (VSS) ................................. 11
2.13 Not Connected (NC) .................................................... 11
2.14 Reserved for Future Use (RFU)................................... 11
2.15 Do Not Use (DNU) ....................................................... 12
2.16 Block Diagrams............................................................ 12
3. Signal Protocols......................................................... 13
3.1 SPI Clock Modes ......................................................... 13
3.2 Command Protocol ...................................................... 14
3.3 Interface States............................................................ 18
3.4 Configuration Register Effects on the Interface ........... 23
3.5 Data Protection ............................................................ 23
4. Electrical Specifications............................................ 24
4.1 Absolute Maximum Ratings ......................................... 24
4.2 Thermal Resistance ..................................................... 24
4.3 Operating Ranges........................................................ 24
4.4 Power-Up and Power-Down ........................................ 25
4.5 DC Characteristics ....................................................... 27
5. Timing Specifications................................................ 28
5.1 Key to Switching Waveforms ....................................... 28
5.2 AC Test Conditions ...................................................... 28
5.3 Reset............................................................................ 29
5.4 SDR AC Characteristics............................................... 31
5.5 DDR AC Characteristics .............................................. 35
6. Physical Interface ...................................................... 38
6.1 SOIC 16-Lead Package ............................................... 38
6.2 FAB024 24-Ball BGA Package .................................... 40
6.3 FAC024 24-Ball BGA Package .................................... 42
Software Interface
7. Address Space Maps................................................. 44
7.1 Overview....................................................................... 44
7.2 Flash Memory Array...................................................... 44
7.3 ID-CFI Address Space .................................................. 45
7.4 JEDEC JESD216 Serial Flash Discoverable Parameters
(SFDP) Space............................................................... 45
7.5 OTP Address Space ..................................................... 45
7.6 Registers....................................................................... 47
8. Data Protection ........................................................... 57
8.1 Secure Silicon Region (OTP)........................................ 57
8.2 Write Enable Command................................................ 57
8.3 Block Protection ............................................................ 58
8.4 Advanced Sector Protection ......................................... 59
9. Commands .................................................................. 62
9.1 Command Set Summary............................................... 64
9.2 Identification Commands .............................................. 69
9.3 Register Access Commands......................................... 71
9.4 Read Memory Array Commands .................................. 81
9.5 Program Flash Array Commands ................................. 95
9.6 Erase Flash Array Commands...................................... 98
9.7 One Time Program Array Commands ........................ 102
9.8 Advanced Sector Protection Commands .................... 102
9.9 Reset Commands ....................................................... 107
9.10 Embedded Algorithm Performance Tables ................. 108
10. Data Integrity ............................................................. 109
10.1 Erase Endurance ........................................................ 109
10.2 Data Retention ............................................................ 109
11. Software Interface Reference .................................. 110
11.1 Command Summary ................................................... 110
11.2 Serial Flash Discoverable Parameters (SFDP) Address
Map............................................................................. 112
11.3 Device ID and Common Flash Interface (ID-CFI) Address
Map............................................................................. 115
11.4 Registers..................................................................... 130
11.5 Initial Delivery State .................................................... 133
Ordering Information
12 Ordering Information ................................................ 134
13. Revision History........................................................ 137
Document Number: 001-98284 Rev. *J
Page 3 of 140


3Pages


S25FL512S 電子部品, 半導体
S25FL512S
1.2.2.3
Configuration Register Freeze Bit
The configuration register Freeze bit CR1[0], locks the state of the Block Protection bits as in prior generations. In the FL-S family it
also locks the state of the configuration register TBPARM bit CR1[2], TBPROT bit CR1[5], and the Secure Silicon Region (OTP)
area.
1.2.2.4
Sector Erase Commands
The command for erasing an 8-kbyte area (two 4-kbyte sectors) is not supported.
The command for erasing a 4-kbyte sector is not supported in the 512-Mbit density FL-S device.
The erase command for 64-kbyte sectors is not supported in the 512-Mbit density FL-S device.
1.2.2.5
Deep Power Down
The Deep Power Down (DPD) function is not supported in FL-S family devices.
The legacy DPD (B9h) command code is instead used to enable legacy SPI memory controllers, that can issue the former DPD
command, to access a new bank address register. The bank address register allows SPI memory controllers that do not support
more than 24 bits of address, the ability to provide higher order address bits for commands, as needed to access the larger address
space of the 256-Mbit density FL-S device. For additional information see Extended Address on page 44.
1.2.2.6
New Features
The FL-S family introduces several new features to SPI category memories:
Extended address for access to higher memory density.
AutoBoot for simpler access to boot code following power up.
Enhanced High Performance read commands using mode bits to eliminate the overhead of SIO instructions when
repeating the same type of read command.
Multiple options for initial read latency (number of dummy cycles) for faster initial access time or higher clock rate read
commands.
DDR read commands for SIO, DIO, and QIO.
Automatic ECC for enhanced data integrity.
Advanced Sector Protection for individually controlling the protection of each sector. This is very similar to the Advanced
Sector Protection feature found in several other Cypress parallel interface NOR memory families.
Document Number: 001-98284 Rev. *J
Page 6 of 140

6 Page



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部品番号部品説明メーカ
S25FL512S

512 Mbit (64 Mbyte) 3.0V SPI Flash Memory

Cypress Semiconductor
Cypress Semiconductor
S25FL512S

512Mbit (64Mbyte) MirrorBit Flash Non-Volatile Memory CMOS 3.0Volt Core

SPANSION
SPANSION


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