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Número de pieza ADM1021A
Descripción Low Cost Microprocessor System Temperature Monitor Microcomputer
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ADM1021A
Low Cost Microprocessor
System Temperature
Monitor Microcomputer
The ADM1021A is a two-channel digital thermometer and
under/overtemperature alarm, intended for use in personal computers
and other systems requiring thermal monitoring and management. The
device can measure the temperature of a microprocessor using
a diode-connected PNP transistor, which can be provided on-chip with
the PentiumIII or similar processors, or can be a low cost discrete
NPN/PNP device, such as the 2N3904/2N3906. A novel measurement
technique cancels out the absolute value of the transistor’s base emitter
voltage so that no calibration is required. The second measurement
channel measures the output of an on-chip temperature sensor to
monitor the temperature of the device and its environment.
The ADM1021A communicates over a two-wire serial interface
compatible with SMBus standards. Under/overtemperature limits can
be programmed into the device over the serial bus, and an ALERT
output signals when the on-chip or remote temperature is out of range.
This output can be used as an interrupt or as an SMBus alert.
Features
Alternative to the ADM1021
On-chip and Remote Temperature Sensing
No Calibration Necessary
1C Accuracy for On-chip Sensor
3C Accuracy for Remote Sensor
Programmable Over/Undertemperature Limits
Programmable Conversion rate
2-wire SMBus Serial Interface
Supports System Management Bus (SMBus) Alert
200 mA Max Operating Current
1 mA Standby Current
3.0 V to 5.5 V Supply
Small 16-lead QSOP Package
This Device is Pb-Free, Halogen Free and is RoHS Compliant
Applications
Desktop Computers
Notebook Computers
Smart Batteries
Industrial Controllers
Telecom Equipment
Instrumentation
http://onsemi.com
QSOP 16
CASE 492
PIN ASSIGNMENT
NC 1
VDD 2
D+ 3
D4
NC 5
ADD1 6
GND 7
GND 8
ADM1021A
(Top View)
16 NC
15 STBY
14 SCLK
13 NC
12 SDATA
11 ALERT
10 ADD0
9 NC
NC = No Connect
MARKING DIAGRAM
1021AA
RQZ
YYWWG
1021AARQZ = Specific Device Code
YY = Year
WW = Work Week
G = Pb-Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 15 of this data sheet.
Semiconductor Components Industries, LLC, 2012
July, 2012 Rev. 9
1
Publication Order Number:
ADM1021A/D

1 page




ADM1021A pdf
ADM1021A
TYPICAL PERFORMANCE CHARACTERISTICS
20
15
10
5 D+ To GND
0
5
10 D+ To VDD
15
20
25
30
1
10 100
LEAKAGE RESISTANCE (MW)
Figure 3. Temperature Error vs. PC Board Track
Resistance
9
100 mV p-p
8
7
6
5
4
3 50 mV p-p
2
1
0 25 mV p-p
1 10 100 1k 10k 100k 1M 10M 100M
FREQUENCY (Hz)
Figure 5. Temperature Error vs. Common-mode
Noise Frequency
14
12
10
8
6
4
2
0
2
2 4 6 8 10 12 14 16 18 20 22 24
CAPACITANCE (nF)
Figure 7. Temperature Error vs. Capacitance
between D+ and D
5
4
250 mV p-p REMOTE
3
2
100 mV p-p REMOTE
1
0
100 1k 10k 100k 1M 10M 100M
FREQUENCY (Hz)
Figure 4. Temperature Error vs. Power Supply
Noise Frequency
3
2
UPPER SPEC LEVEL
1
DEV10
0
1
LOWER SPEC LEVEL
2
3
50 60 70 80 90 100 110 120
TEMPERATURE (C)
Figure 6. Temperature Error vs. Pentium) III
Temperature
70
60
50
40
30
20 VDD = 3.3 V
10
VDD = 5 V
0
1 5 10 25 50 75 100 250 500 750 1000
SCLK FREQUENCY (kHz)
Figure 8. Standby Supply Current vs. Clock
Frequency
http://onsemi.com
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ADM1021A arduino
ADM1021A
Table 11. DEVICE ADDRESSES (Note 1)
ADD0
ADD1
Device Address
0 0 0011 000
0 NC 0011 001
0 1 0011 010
NC 0 0101 001
NC NC 0101 010
NC 1 0101 011
1 0 1001 100
1 NC 1001 101
1 1 1001 110
1. ADD0 and ADD1 are sampled at powerup only.
The serial bus protocol operates as follows:
1. The master initiates data transfer by establishing a
start condition, defined as a high-to-low transition
on the serial data line SDATA, while the serial
clock line SCLK remains high. This indicates that
an address/data stream will follow. All slave
peripherals connected to the serial bus respond to
the START condition and shift in the next eight
bits, consisting of a 7-bit address (MSB first) plus
an R/W bit, which determines the direction of the
data transfer, that is, whether data will be written
to or read from the slave device.
The peripheral whose address corresponds to the
transmitted address responds by pulling the data
line low during the low period before the ninth
clock pulse, known as the Acknowledge Bit. All
other devices on the bus now remain idle while the
selected device waits for data to be read from or
written to it. If the R/W bit is a 0, the master writes
to the slave device. If the R/W bit is a 1, the
master reads from the slave device.
2. Data is sent over the serial bus in sequences of
nine clock pulses, eight bits of data followed by an
Acknowledge Bit from the slave device.
Transitions on the data line must occur during the
low period of the clock signal and remain stable
during the high period, because a low-to-high
transition when the clock is high can be interpreted
as a stop signal. The number of data bytes that can
be transmitted over the serial bus in a single read
or write operation is limited only by what the
master and slave devices can handle.
3. When all data bytes have been read or written,
stop conditions are established. In write mode, the
master pulls the data line high during the 10th
clock pulse to assert a stop condition. In read
mode, the master device overrides the
acknowledge bit by pulling the data line high
during the low period before the ninth clock pulse.
This is known as No Acknowledge. The master
then takes the data line low during the low period
before the 10th clock pulse, then high during the
10th clock pulse to assert a stop condition.
Any number of bytes of data can be transferred over the
serial bus in one operation, but it is not possible to mix read
and write in one operation, because the type of operation is
determined at the beginning and cannot subsequently be
changed without starting a new operation.
For the ADM1021A, write operations contain either one
or two bytes, while read operations contain one byte.
To write data to one of the device data registers or read
data from it, the address pointer register must be set so that
the correct data register is addressed, data can then be written
into that register or read from it. The first byte of a write
operation always contains a valid address that is stored in the
address pointer register. If data is to be written to the device,
the write operation contains a second data byte that is written
to the register selected by the address pointer register.
This is illustrated in Figure 14. The device address is sent
over the bus followed by R/W set to 0. This is followed by
two data bytes. The first data byte is the address of the
internal data register to be written to, which is stored in the
address pointer register. The second data byte is the data to
be written to the internal data register.
SCLK
1
91
9
SDATA
A6
START BY
MASTER
A5 A4 A3 A2 A1 A0 R/W
D7
ACK. BY
FRAME 1
ADM1021A
SERIAL BUS ADDRESS BYTE
D6 D5 D4 D3 D2 D1 D0
ACK. BY
FRAME 2
ADM1021A
ADDRESS POINTER REGISTER BYTE
SCLK (CONTINUED)
1
9
SDATA (CONTINUED)
D7 D6 D5 D4 D3 D2 D1 D0
FRAME 3
DATA BYTE
ACK. BY
ADM1021A
STOP BY
MASTER
Figure 14. Writing a Register Address to the Address Pointer Register, then Writing Data to the Selected Register
http://onsemi.com
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