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74HC157 の電気的特性と機能

74HC157のメーカーはNXP Semiconductorsです、この部品の機能は「High-speed CMOS Quad 2-input Multiplexer IC」です。


製品の詳細 ( Datasheet PDF )

部品番号 74HC157
部品説明 High-speed CMOS Quad 2-input Multiplexer IC
メーカ NXP Semiconductors
ロゴ NXP Semiconductors ロゴ 




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74HC157 Datasheet, 74HC157 PDF,ピン配置, 機能
74HC157; 74HCT157
Quad 2-input multiplexer
Rev. 8 — 28 December 2015
Product data sheet
1. General description
The 74HC157; 74HCT157 is a high-speed Si-gate CMOS device and is pin compatible
with Low-power Schottky TTL. It is specified in compliance with JEDEC standard no. 7A.
The 74HC/HCT157 are quad 2-input multiplexers which select 4 bits of data from two
sources under the control of a common data select input (S). The enable input (E) is
active LOW. When E is HIGH, all of the outputs (1Y to 4Y) are forced LOW regardless of
all other input conditions.
Moving the data from two groups of registers to four common output buses is a common
use of the 74HC/HCT157. The state of the common data select input (S) determines the
particular register from which the data comes. It can also be used as function generator.
The device is useful for implementing highly irregular logic by generating any four of the
16 different functions of two variables with one variable common. The 74HC/HCT157 is
logic implementation of a 4-pole, 2-position switch, where the position of the switch is
determined by the logic levels applied to S.
The logic equations are:
1Y = E (1I1 S + 1I0 S)
2Y = E (2I1 S + 2I0 S)
3Y = E (3I1 S + 3I0 S)
4Y = E (4I1 S + 4I0 S)
The 74HC/HCT157 is identical to the 74HC158 but has non-inverting (true) outputs.
2. Features and benefits
Low-power dissipation
Complies with JEDEC standard no. 7A
Input levels:
For 74HC157: CMOS level
For 74HCT157: TTL level
Non-inverting data path
ESD protection:
HBM JESD22-A114F exceeds 2 000 V
MM JESD22-A115-A exceeds 200 V
Specified from 40 C to +85 C and from 40 C to +125 C

1 Page





74HC157 pdf, ピン配列
NXP Semiconductors
74HC157; 74HCT157
Quad 2-input multiplexer
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Fig 3. Logic symbol
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5. Pinning information
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Fig 5. Pin configuration SO16, (T)SSOP16
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Fig 4. IEC logic symbol
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(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 6. Pin configuration DHVQFN16
74HC_HCT157
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 28 December 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
3 of 18


3Pages


74HC157 電子部品, 半導体
NXP Semiconductors
74HC157; 74HCT157
Quad 2-input multiplexer
Table 6. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Tamb = 25 C
Tamb = 40 C
to +85 C
Min Typ Max Min Max
CI input
capacitance
- 3.5 -
-
-
74HCT157
VIH HIGH-level VCC = 4.5 V to 5.5 V
input voltage
2.0 1.6 -
2.0
-
VIL LOW-level VCC = 4.5 V to 5.5 V
input voltage
- 1.2 0.8
-
0.8
VOH HIGH-level
VI = VIH or VIL; VCC = 4.5 V
output voltage
IO = 20 A
4.4 4.5 -
4.4
-
IO = 4 mA
3.98 4.32 - 3.84
-
VOL LOW-level
VI = VIH or VIL; VCC = 4.5 V
output voltage
IO = 20 A
- 0 0.1 -
0.1
IO = 4.0 mA
- 0.15 0.26 -
0.33
II
input leakage VI = VCC or GND; VCC = 5.5 V -
- 0.1 -
1.0
current
ICC
ICC
supply current VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
- - 8.0
additional
supply current
VI = VCC 2.1 V;
other inputs at VCC or GND;
VCC = 4.5 V to 5.5 V; IO = 0 A
per input pin; nI0, nI1 inputs - 100 360
-
-
80
450
per input pin; E input
- 60 216 -
270
per input pin; S input
- 100 360 -
450
CI input
capacitance
- 3.5 -
-
-
Tamb = 40 C to Unit
+125 C
Min Max
- - pF
2.0 - V
- 0.8 V
4.4 - V
3.7 - V
- 0.1 V
- 0.4 V
- 1.0 A
- 160 A
- 490 A
- 294 A
- 490 A
- - pF
74HC_HCT157
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 28 December 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
6 of 18

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