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GS8342T08BGD の電気的特性と機能

GS8342T08BGDのメーカーはGSI Technologyです、この部品の機能は「36Mb SigmaDDR-II Burst of 2 SRAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 GS8342T08BGD
部品説明 36Mb SigmaDDR-II Burst of 2 SRAM
メーカ GSI Technology
ロゴ GSI Technology ロゴ 




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GS8342T08BGD Datasheet, GS8342T08BGD PDF,ピン配置, 機能
GS8342T08/09/18/36BD-400/350/333/300/250
165-Bump BGA
Commercial Temp
Industrial Temp
36Mb SigmaDDR-IITM
Burst of 2 SRAM
400 MHz–250 MHz
1.8 V VDD
1.8 V and 1.5 V I/O
Features
• Simultaneous Read and Write SigmaDDR™ Interface
• Common I/O bus
• JEDEC-standard pinout and package
• Double Data Rate interface
• Byte Write (x36, x18 and x9) and Nybble Write (x8) function
• Burst of 2 Read and Write
• 1.8 V +100/–100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
• Pipelined read operation with self-timed Late Write
• Fully coherent read and write pipelines
• ZQ pin for programmable output drive strength
• IEEE 1149.1 JTAG-compliant Boundary Scan
• Pin-compatible with present 9Mb, 18Mb, 36Mb and 72Mb
devices
• 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package
• RoHS-compliant 165-bump BGA package available
SigmaDDRFamily Overview
The GS8342T08/09/18/36BD are built in compliance with the
SigmaDDR-II SRAM pinout standard for Common I/O
synchronous SRAMs. They are 37,748,736-bit (36Mb)
SRAMs. The GS8342T08/09/18/36BD SigmaDDR-II SRAMs
are just one element in a family of low power, low voltage
HSTL I/O SRAMs designed to operate at the speeds needed to
implement economical high performance networking systems.
Clocking and Addressing Schemes
The GS8342T08/09/18/36BD SigmaDDR-II SRAMs are
synchronous devices. They employ two input register clock
inputs, K and K. K and K are independent single-ended clock
inputs, not differential inputs to a single differential clock input
buffer. The device also allows the user to manipulate the
output register clock inputs quasi independently with the C and
C clock inputs. C and C are also independent single-ended
clock inputs, not differential inputs. If the C clocks are tied
high, the K clocks are routed internally to fire the output
registers instead.
Each internal read and write operation in a SigmaDDR-II B2
RAM is two times wider than the device I/O bus. An input data
bus de-multiplexer is used to accumulate incoming data before
it is simultaneously written to the memory array. An output
data multiplexer is used to capture the data produced from a
single memory array read and then route it to the appropriate
output drivers as needed.
When a new address is loaded into a x18 or x36 version of the
part, A0 is used to initialize the pointers that control the data
multiplexer / de-multiplexer so the RAM can perform "critical
word first" operations. From an external address point of view,
regardless of the starting point, the data transfers always follow
the same sequence {0, 1} or {1, 0} (where the digits shown
represent A0).
Unlike the x18 and x36 versions, the input and output data
multiplexers of the x8 and x9 versions are not preset by
address inputs and therefore do not allow "critical word first"
operations. The address fields of the x8 and x9 SigmaDDR-II
B2 RAMs are one address pin less than the advertised index
depth (e.g., the 4M x 8 has a 2M addressable index, and A0 is
not an accessible address pin).
Parameter Synopsis
tKHKH
tKHQV
-400
2.5 ns
0.45 ns
-350
2.86 ns
0.45 ns
-333
3.0 ns
0.45 ns
-300
3.3 ns
0.45 ns
-250
4.0 ns
0.45 ns
Rev: 1.02 6/2012
1/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology

1 Page





GS8342T08BGD pdf, ピン配列
GS8342T08/09/18/36BD-400/350/333/300/250
2M x 18 SigmaDDR-II SRAM—Top View
123456789
A
CQ
NC/SA
(72Mb)
SA
R/W BW1
K
NC/SA
(144Mb)
LD
SA
B
NC DQ9 NC
SA
NC/SA
(288Mb)
K
BW0 SA
NC
C NC NC NC VSS SA SA0 SA VSS NC
D NC NC DQ10 VSS VSS VSS VSS VSS NC
E
NC
NC
DQ11
VDDQ
VSS
VSS
VSS VDDQ NC
F
NC DQ12 NC
VDDQ
VDD
VSS
VDD VDDQ NC
G
NC
NC
DQ13
VDDQ
VDD
VSS
VDD VDDQ NC
H
Doff
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
J
NC
NC
NC
VDDQ
VDD
VSS
VDD VDDQ NC
K
NC
NC
DQ14
VDDQ
VDD
VSS
VDD VDDQ NC
L
NC DQ15 NC
VDDQ
VSS
VSS
VSS VDDQ NC
M NC NC NC VSS VSS VSS VSS VSS NC
N
NC
NC DQ16 VSS
SA
SA
SA
VSS NC
P NC NC DQ17 SA SA C SA SA NC
R
TDO TCK
SA
SA
SA
C
SA SA SA
11 x 15 Bump BGA—13 x 15 mm Body—1 mm Bump Pitch
Notes:
1. BW0 controls writes to DQ0:DQ8; BW1 controls writes to DQ9:DQ17.
2. A2, A7, and B5 are the expansion addresses.
10
SA
NC
DQ7
NC
NC
NC
NC
VREF
DQ4
NC
NC
DQ1
NC
NC
TMS
11
CQ
DQ8
NC
NC
DQ6
DQ5
NC
ZQ
NC
DQ3
DQ2
NC
NC
DQ0
TDI
Rev: 1.02 6/2012
3/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology


3Pages


GS8342T08BGD 電子部品, 半導体
GS8342T08/09/18/36BD-400/350/333/300/250
Pin Description Table
Symbol
Description
Type Comments
SA
Synchronous Address Inputs
Input —
R/W
Synchronous Read/Write
Input
Read: Active High
Write: Active Low
BW0–BW3
Synchronous Byte Writes
Input
Active Low
x18/x36 only
NW0–NW1
Nybble Write Control Pin
Input
Active Low
x8 only
LD
Synchronous Load Pin
Input Active Low
K
Input Clock
Input Active High
K
Input Clock
Input Active Low
C
Output Clock
Input Active High
C
Output Clock
Input Active Low
TMS
Test Mode Select
Input —
TDI
Test Data Input
Input —
TCK
Test Clock Input
Input —
TDO
Test Data Output
Output
VREF
HSTL Input Reference Voltage
Input —
ZQ
Output Impedance Matching Input
Input
MCL
Must Connect Low
——
DQ
Data I/O
Input/Output
Three State
Doff
Disable DLL when low
Input Active Low
CQ
Output Echo Clock
Output
CQ
Output Echo Clock
Output
VDD
Power Supply
Supply
1.8 V Nominal
VDDQ
Isolated Output Buffer Supply
Supply
1.8 V or 1.5 V Nominal
VSS
Power Supply: Ground
Supply
NC
No Connect
——
Notes:
1. NC = Not Connected to die or any other pin
2. When ZQ pin is directly connected to VDDQ, output impedance is set to minimum value and it cannot be connected to ground or left
unconnected.
3. C, C, K, K cannot be set to VREF voltage.
Rev: 1.02 6/2012
6/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology

6 Page



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部品番号部品説明メーカ
GS8342T08BGD

36Mb SigmaDDR-II Burst of 2 SRAM

GSI Technology
GSI Technology


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