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GS8342S09BGD の電気的特性と機能

GS8342S09BGDのメーカーはGSI Technologyです、この部品の機能は「36Mb SigmaSIO DDR-II Burst of 2 SRAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 GS8342S09BGD
部品説明 36Mb SigmaSIO DDR-II Burst of 2 SRAM
メーカ GSI Technology
ロゴ GSI Technology ロゴ 




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GS8342S09BGD Datasheet, GS8342S09BGD PDF,ピン配置, 機能
GS8342S08/09/18/36BD-400/350/333/300/250
165-Bump BGA
Commercial Temp
Industrial Temp
36Mb SigmaSIO DDR-IITM
Burst of 2 SRAM
400 MHz–250 MHz
1.8 V VDD
1.8 V and 1.5 V I/O
Features
• Simultaneous Read and Write SigmaSIO™ Interface
• JEDEC-standard pinout and package
• Dual Double Data Rate interface
• Byte Write controls sampled at data-in time
• DLL circuitry for wide output data valid window and future
frequency scaling
• Burst of 2 Read and Write
• 1.8 V +100/–100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
• Pipelined read operation
• Fully coherent read and write pipelines
• ZQ mode pin for programmable output drive strength
• IEEE 1149.1 JTAG-compliant Boundary Scan
• 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package
• RoHS-compliant 165-bump BGA package available
SigmaSIOFamily Overview
GS8342S08/09/18/36BD are built in compliance with the
SigmaSIO DDR-II SRAM pinout standard for Separate I/O
synchronous SRAMs. They are 37,748,736-bit (36Mb)
SRAMs. These are the first in a family of wide, very low
voltage HSTL I/O SRAMs designed to operate at the speeds
needed to implement economical high performance
networking systems.
Clocking and Addressing Schemes
A Burst of 2 SigmaSIO DDR-II SRAM is a synchronous
device. It employs dual input register clock inputs, K and K.
The device also allows the user to manipulate the output
register clock input quasi independently with dual output
register clock inputs, C and C. If the C clocks are tied high, the
K clocks are routed internally to fire the output registers
instead. Each Burst of 2 SigmaSIO DDR-II SRAM also
supplies Echo Clock outputs, CQ and CQ, which are
synchronized with read data output. When used in a source
synchronous clocking scheme, the Echo Clock outputs can be
used to fire input registers at the data’s destination.
Each internal read and write operation in a SigmaSIO DDR-II
B2 RAM is two times wider than the device I/O bus. An input
data bus de-multiplexer is used to accumulate incoming data
before it is simultaneously written to the memory array. An
output data multiplexer is used to capture the data produced
from a single memory array read and then route it to the
appropriate output drivers as needed. Therefore, the address
field of a SigmaSIO DDR-II B2 is always one address pin less
than the advertised index depth (e.g., the 4M x 8 has an 2M
addressable index).
Parameter Synopsis
tKHKH
tKHQV
-400
2.5 ns
0.45 ns
-350
2.86 ns
0.45 ns
-333
3.0 ns
0.45 ns
-300
3.3 ns
0.45 ns
-250
4.0 ns
0.45 ns
Rev: 1.02 6/2012
1/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology

1 Page





GS8342S09BGD pdf, ピン配列
GS8342S08/09/18/36BD-400/350/333/300/250
4M x 9 SigmaQuad SRAM—Top View
123456789
A
CQ
NC/SA
(72Mb)
SA
R/W
NC
K
NC/SA
(144Mb)
LD
SA
B
NC
NC
NC
SA
NC/SA
(288Mb)
K
BW0 SA
NC
C NC NC NC VSS SA SA SA VSS NC
D NC D5 NC VSS VSS VSS VSS VSS NC
E
NC
NC
Q5
VDDQ
VSS
VSS
VSS VDDQ NC
F
NC
NC
NC
VDDQ
VDD
VSS
VDD VDDQ NC
G
NC D6
Q6
VDDQ
VDD
VSS
VDD VDDQ NC
H
Doff
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
J
NC
NC
NC
VDDQ
VDD
VSS
VDD VDDQ NC
K
NC
NC
NC
VDDQ
VDD
VSS
VDD VDDQ NC
L
NC
Q7
D7
VDDQ
VSS
VSS
VSS VDDQ NC
M NC NC NC VSS VSS VSS VSS VSS NC
N NC D8 NC VSS SA SA SA VSS NC
P NC NC Q8 SA SA C SA SA NC
R
TDO TCK
SA
SA
SA
C
SA SA SA
11 x 15 Bump BGA—13 x 15 mm Body—1 mm Bump Pitch
Notes:
1. BW0 controls writes to D0:D7.
2. A2, A7, and B5 are the expansion addresses.
10
SA
NC
NC
NC
D3
NC
NC
VREF
Q2
NC
NC
NC
NC
D0
TMS
11
CQ
Q4
D4
NC
Q3
NC
NC
ZQ
D2
NC
Q1
D1
NC
Q0
TDI
Rev: 1.02 6/2012
3/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology


3Pages


GS8342S09BGD 電子部品, 半導体
GS8342S08/09/18/36BD-400/350/333/300/250
Pin Description Table
Symbol
Description
Type Comments
SA
Synchronous Address Inputs
Input —
R/W
Read/Write Contol Pin
Input Write Active Low; Read Active High
NW0–NW1
Synchronous Nybble Writes
Input
Active Low
x08 Version
BW0–BW1
Synchronous Byte Writes
Input
Active Low
x18 Version
BW0–BW3
Synchronous Byte Writes
Input
Active Low
x36 Version
K
Input Clock
Input Active High
C
Output Clock
Input Active High
TMS
Test Mode Select
Input —
TDI
Test Data Input
Input —
TCK
Test Clock Input
Input —
TDO
Test Data Output
Output
VREF
HSTL Input Reference Voltage
Input —
ZQ
Output Impedance Matching Input
Input
K
Input Clock
Input Active Low
C
Output Clock
Input Active Low
DOFF
DLL Disable
Input Active Low
LD
Synchronous Load Pin
Input Active Low
CQ
Output Echo Clock
Output
CQ
Output Echo Clock
Output
Dn
Synchronous Data Inputs
Input —
Qn
Synchronous Data Outputs
Output
VDD
Power Supply
Supply
1.8 V Nominal
VDDQ
Isolated Output Buffer Supply
Supply
1.8 or 1.5 V Nominal
VSS
Power Supply: Ground
Supply
NC
No Connect
——
Notes:
1. C, C, K, or K cannot be set to VREF voltage.
2. When ZQ pin is directly connected to VDDQ, output impedance is set to minimum value and it cannot be connected to ground or left
unconnected.
3. NC = Not Connected to die or any other pin
Rev: 1.02 6/2012
6/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology

6 Page



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部品番号部品説明メーカ
GS8342S09BGD

36Mb SigmaSIO DDR-II Burst of 2 SRAM

GSI Technology
GSI Technology


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