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GS4576C18L の電気的特性と機能

GS4576C18LのメーカーはGSI Technologyです、この部品の機能は「576Mb CIO Low Latency DRAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 GS4576C18L
部品説明 576Mb CIO Low Latency DRAM
メーカ GSI Technology
ロゴ GSI Technology ロゴ 




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GS4576C18L Datasheet, GS4576C18L PDF,ピン配置, 機能
GS4576C09/18/36L
144-Ball BGA
Commercial Temp
Industrial Temp
64M x 9, 32M x 18, 16M x 36
576Mb CIO Low Latency DRAM (LLDRAM II)
533 MHz300 MHz
2.5 V VEXT
1.8 V VDD
1.5 V or 1.8 V VDDQ
Features
• Pin- and function-compatible with Micron RLDRAM® II
• 533 MHz DDR operation (1.067Gb/s/pin data rate)
• 38.4 Gb/s peak bandwidth (x36 at 533 MHz clock frequency)
• 16M x 36, 32M x 18, and 64M x 9 organizations available
• 8 banks
• Reduced cycle time (15 ns at 533 MHz)
• Address Multiplexing (Nonmultiplexed address option
available)
• SRAM-type interface
• Programmable Read Latency (RL), row cycle time, and burst
sequence length
• Balanced Read and Write Latencies in order to optimize data
bus utilization
• Data mask for Write commands
• Differential input clocks (CK, CK)
• Differential input data clocks (DKx, DKx)
• On-chip DLL generates CK edge-aligned data and output
data clock signals
• Data valid signal (QVLD)
• 32 ms refresh (16K refresh for each bank; 128K refresh
command must be issued in total each 32 ms)
• 144-ball BGA package
• HSTL I/O (1.5 V or 1.8 V nominal)
• 25–60matched impedance outputs
• 2.5 V VEXT, 1.8 V VDD, 1.5 V or 1.8 V VDDQ I/O
• On-die termination (ODT) RTT
• Commerical and Industrial Temperature
Commercial (+0° TC +95°C)
Industrial (–40° TC +95°C)
Introduction
The GSI Technology 576Mb Low Latency DRAM
(LLDRAM II) is a high speed memory device designed for
high address rate data processing typically found in networking
and telecommunications applications. The 8-bank architecture
and low tRC allows access rates formerly only found in
SRAMs.
The Double Data Rate (DDR) I/O interface provides high
bandwidth data transfers, clocking out two beats of data per
clock cycle at the I/O balls. Source-synchronous clocking can
be implemented on the host device with the provided free-
running data output clock.
Commands, addresses, and control signals are single data rate
signals clocked in by the True differential input clock
transition, while input data is clocked in on both crossings of
the input data clock(s).
Read and Write data transfers always in short bursts. The burst
length is programmable to 2, 4 or 8 by setting the Mode
Register.
The device is supplied with 2.5 V VEXT and 1.8 V VDD for the
core, and 1.5 V or 1.8 V for the HSTL output drivers.
Internally generated row addresses facilitate bank-scheduled
refresh.
The device is delivered in an efficent BGA 144-ball package.
Rev: 1.04 11/2013
1/62
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology

1 Page





GS4576C18L pdf, ピン配列
32M x 18 Ball Assignments—144-Ball BGA—Top View
GS4576C09/18/36L
1 2 3 4 5 6 7 8 9 10 11 12
A VREF VSS VEXT VSS
VSS VEXT TMS TCK
B
VDD DNU4 DQ4
VSS
VSS DQ0 DNU4 VDD
C VTT DNU4 DQ5 VDDQ
VDDQ
DQ1 DNU4
VTT
D
A221 DNU4 DQ6
VSS
VSS QK0 QK0 VSS
E A212 DNU4 DQ7 VDDQ
VDDQ DQ2 DNU4 A20
F A5 DNU4 DQ8 VSS
VSS DQ3 DNU4 QVLD
G A8 A6 A7 VDD
VDD A2 A1 A0
H B2 A9 VSS VSS
VSS VSS A4 A3
J NF3 NF3 VDD VDD
VDD VDD B0 CK
K DK DK VDD VDD
VDD VDD B1 CK
L REF CS VSS VSS
VSS VSS A14 A13
M WE A16 A17 VDD
VDD A12 A11 A10
N A18 DNU4 DQ14 VSS
VSS DQ9 DNU4 A19
P A15 DNU4 DQ15 VDDQ
VDDQ DQ10 DNU4
DM
R VSS QK1 QK1 VSS
VSS DQ11 DNU4 VSS
T VTT DNU4 DQ16 VDDQ
VDDQ DQ12 DNU4
VTT
U VDD DNU4 DQ17 VSS
VSS DQ13 DNU4 VDD
V VREF ZQ VEXT VSS
VSS VEXT TDO
Notes:
1. Reserved for future use. This pin may be connected to GND.
2. Reserved for future use. This pin may have parasitic characteristics of an address input signal. It may be connected to GND.
3. No function. This pin may have parasitic characteristics of a clock input signal. It may be connected to GND.
4. Do not use. This pin may have parasitic characteristics of an I/O. It may be connected to GND.
TDI
Rev: 1.04 11/2013
3/62
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology


3Pages


GS4576C18L 電子部品, 半導体
GS4576C09/18/36L
Ball Descriptions (Continued)
Symbol
QVLD
Type
Output
Description
Data Valid—The QVLD pin indicates valid output data. QVLD is edge-aligned with QKx and QKx.
TDO
Output
IEEE 1149.1 Test Output—JTAG output. This ball may be left as no connect if the JTAG function is not
used.
VDD
Supply
Power Supply—Nominally, 1.8 V. See the DC Electrical Characteristics and Operating Conditions
section for range.
VDDQ
Supply
DQ Power Supply—Nominally, 1.5 V or 1.8 V. Isolated on the device for improved noise immunity. See
the DC Electrical Characteristics and Operating Conditions section for range.
VEXT
Supply
Power Supply—Nominally, 2.5 V. See the DC Electrical Characteristics and Operating Conditions
section for range.
VSS Supply Ground
VTT
Power Supply—Isolated termination supply. Nominally, VDDQ/2. See the DC Electrical Characteristics
and Operating Conditions section for range.
A22 — Reserved for Future Use—This signal is not connected and may be connected to ground.
DNU — Do Not Use—These balls may be connected to ground.
NF — No Function—These balls can be connected to ground.
Rev: 1.04 11/2013
6/62
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology

6 Page



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部品番号部品説明メーカ
GS4576C18GL

576Mb CIO Low Latency DRAM

GSI Technology
GSI Technology
GS4576C18L

576Mb CIO Low Latency DRAM

GSI Technology
GSI Technology


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