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GS81314LQ36GK の電気的特性と機能

GS81314LQ36GKのメーカーはGSI Technologyです、この部品の機能は「144Mb SigmaQuad-IVe Burst of 2 Multi-Bank ECCRAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 GS81314LQ36GK
部品説明 144Mb SigmaQuad-IVe Burst of 2 Multi-Bank ECCRAM
メーカ GSI Technology
ロゴ GSI Technology ロゴ 




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GS81314LQ36GK Datasheet, GS81314LQ36GK PDF,ピン配置, 機能
GS81314LQ18/36GK-133/120/106
260-Pin BGA
Com & Ind Temp
HSTL I/O
144Mb SigmaQuad-IVe™
Burst of 2 Multi-Bank ECCRAM™
Up to 1333 MHz
1.25V ~ 1.3V VDD
1.2V ~ 1.3V VDDQ
Features
• 4Mb x 36 and 8Mb x 18 organizations available
• Organized as 16 logical memory banks
• 1333 MHz maximum operating frequency
• 2.666 BT/s peak transaction rate (in billions per second)
• 192 Gb/s peak data bandwidth (in x36 devices)
• Separate I/O DDR Data Buses
• Non-multiplexed DDR Address Bus
• Two operations - Read and Write - per clock cycle
• Certain address/bank restrictions on Read and Write ops
• Burst of 2 Read and Write operations
• 6 cycle Read Latency
• On-chip ECC with virtually zero SER
• Loopback signal timing training capability
• 1.25V ~ 1.3V nominal core voltage
• 1.2V ~ 1.3V HSTL I/O interface
• Configuration registers
• Configurable ODT (on-die termination)
• ZQ pin for programmable driver impedance
• ZT pin for programmable ODT impedance
• IEEE 1149.1 JTAG-compliant Boundary Scan
• 260-pin, 14 mm x 22 mm, 1 mm ball pitch, 6/6 RoHS-
compliant BGA package
SigmaQuad-IVeFamily Overview
SigmaQuad-IVe ECCRAMs are the Separate I/O half of the
SigmaQuad-IVe/SigmaDDR-IVe family of high performance
ECCRAMs. Although similar to GSI's third generation of
networking SRAMs (the SigmaQuad-IIIe/SigmaDDR-IIIe
family), these fourth generation devices offer several new
features that help enable significantly higher performance.
Clocking and Addressing Schemes
The GS81314LQ18/36GK SigmaQuad-IVe ECCRAMs are
synchronous devices. They employ three pairs of positive and
negative input clocks; one pair of master clocks, CK and CK,
and two pairs of write data clocks, KD[1:0] and KD[1:0]. All
six input clocks are single-ended; that is, each is received by a
dedicated input buffer.
CK and CK are used to latch address and control inputs, and to
control all output timing. KD[1:0] and KD[1:0] are used solely
to latch data inputs.
Each internal read and write operation in a SigmaQuad-IVe B2
ECCRAM is two times wider than the device I/O bus. An input
data bus de-multiplexer is used to accumulate incoming data
before it is simultaneously written to the memory array. An
output data multiplexer is used to capture the data produced
from a single memory array read and then route it to the
appropriate output drivers as needed. Therefore, the address
field of a SigmaQuad-IVe B2 ECCRAM is always one address
pin less than the advertised index depth (e.g. the 8M x 18 has
4M addressable index).
On-Chip Error Correction Code
GSI's ECCRAMs implement an ECC algorithm that detects
and corrects all single-bit memory errors, including those
induced by SER events such as cosmic rays, alpha particles,
etc. The resulting Soft Error Rate of these devices is
anticipated to be <0.002 FITs/Mb — a 5-order-of-magnitude
improvement over comparable SRAMs with no on-chip ECC,
which typically have an SER of 200 FITs/Mb or more.
All quoted SER values are at sea level in New York City.
Speed Grade
-133
-120
-106
Parameter Synopsis
Max Operating Frequency
1333 MHz
1200 MHz
1066 MHz
Read Latency
6 cycles
6 cycles
6 cycles
VDD
1.2V to 1.35V
1.2V to 1.35V
1.2V to 1.35V
Rev: 1.09 5/2016
1/40
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2014, GSI Technology

1 Page





GS81314LQ36GK pdf, ピン配列
GS81314LQ18/36GK-133/120/106
4M x 36 Pinout (Top View)
1 2 3 4 5 6 7 8 9 10 11 12 13
A
VDD
VDDQ
VDD
VDDQ
NC
(RSVD)
MCL
(CFG)
MRW
ZQ
PZT1 VDDQ VDD VDDQ VDD
B
VSS
Q35
VSS
D35
MCL
MCL
(B4M)
NC
(RSVD)
MCH
(SIOM)
PZT0
D0
VSS Q0
VSS
C Q26 VDDQ D26 VDDQ VSS SA13 VDD SA14 VSS VDDQ D9 VDDQ Q9
D
VSS
Q34
VSS
D34
SA19
VDDQ
NC
(288 Mb)
VDDQ
SA20
D1
VSS
Q1
VSS
E Q25 VDDQ D25 VDD VSS SA11 VSS SA12 VSS VDD D10 VDDQ Q10
F VSS Q33 VSS D33 SA17 VDD VDDQ VDD SA18 D2 VSS Q2 VSS
G Q24 Q32 D24 D32 VSS SA9 MZT1 SA10 VSS D3 D11 Q3 Q11
H Q23 VDDQ D23 VDDQ SA15 VDDQ W VDDQ SA16 VDDQ D12 VDDQ Q12
J VSS Q31 VSS D31 VSS SA7 VSS SA8 VSS D4 VSS Q4 VSS
K CQ1 VDDQ VREF VDD KD1 VDD CK VDD KD0 VDD VREF VDDQ CQ0
L CQ1 VSS QVLD1 VSS KD1 VDDQ CK VDDQ KD0 VSS QVLD0 VSS CQ0
M VSS Q22 VSS D22 VSS SA5 VSS SA6 VSS D13 VSS Q13 VSS
N Q30 VDDQ D30 VDDQ PLL VDDQ R VDDQ MCL VDDQ D5 VDDQ Q5
P Q29 Q21 D29 D21 VSS SA3 MZT0 SA4 VSS D14 D6 Q14 Q6
R VSS Q20 VSS D20 MCH VDD VDDQ VDD RST D15 VSS Q15 VSS
T Q28 VDDQ D28 VDD VSS SA1 VSS SA2 VSS VDD D7 VDDQ Q7
U
VSS
Q19
VSS
D19
NC
(576 Mb)
VDDQ
NC
(RSVD)
VDDQ
NC
(1152 Mb)
D16
VSS
Q16
VSS
V
Q27 VDDQ D27 VDDQ VSS
NUI
(x18)
VDD
SA0
(B2)
VSS VDDQ D8 VDDQ Q8
W VSS Q18 VSS D18 TCK MCL RCS MCL TMS D17 VSS Q17 VSS
Y
VDD VDDQ VDD VDDQ TDO
ZT
NC
(RSVD)
MCL
TDI
VDDQ VDD VDDQ VDD
Notes:
1. Pins 5B, 6W, 8W, 8Y, and 9N must be tied Low in this device.
2. Pin 5R must be tied High in this device.
3. Pin 6A is defined as mode pin CFG in the pinout standard. It must be tied Low in this device to select x36 configuration.
4. Pin 6B is defined as mode pin B4M in the pinout standard. It must be tied Low in this device to select Burst-of-2 configuration.
5. Pin 8B is defined as mode pin SIOM in the pinout standard. It must be tied High in this device to select Separate I/O configuration.
6. Pin 6V is defined as address pin SA for x18 devices. It is unused in this device, and must be left unconnected or driven Low.
7. Pin 8V is defined as address pin SA for B2 devices. It is used in this device.
8. Pin 7D is reserved as address pin SA for 288 Mb devices. It is a true no connect in this device.
9. Pin 5U is reserved as address pin SA for 576 Mb devices. It is a true no connect in this device.
10. Pin 9U is reserved as address pin SA for 1152 Mb devices. It is a true no connect in this device.
Rev: 1.09 5/2016
3/40
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2014, GSI Technology


3Pages


GS81314LQ36GK 電子部品, 半導体
GS81314LQ18/36GK-133/120/106
Initialization Summary
Prior to functional use, these devices must first be initialized and configured. The steps described below will ensure that the
internal logic has been properly reset, and that functional timing parameters have been configured.
Flow Chart
Power-Up
Reset SRAM
Wait for Calibrations
Enable PLL,
Wait for Lock
Training
Required?
Yes
No
Address / Control
Input Training
Read Data
Output Training
Write Data
Input Training
Additional
Configuration
Normal Operation
Yes Train No
Again?
Notes:
1. MZT[1:0] and PZT[1:0] mode pins are used to set the default ODT state of all
input groups at power-up, and whenever RST is asserted High. The ODT state
for each input group can be changed any time thereafter using Register Write
Mode to program certain bits in the Configuration Registers.
2. Calibrations are performed for driver impedance, ODT impedance, and the PLL
current source immediately after RST is de-asserted Low. The calibrations can
take up to 384K cycles total. See the Power-Up and Reset Requirements section
for more information.
3. The PLL can be enabled by the PLL pin, or by the PLL Enable (PLE) bit in the
Configuration Registers. See the PLL Operation section for more information.
4. If the PLE register bit is used to enable the PLL, then Register Write Mode will
likely have to be utilized in the “Asynchronous, Pre-Input Training” method in
order to change the state of the bit, since Address / Control Input Training has
not yet been performed. See the Configuration Registers section for more infor-
mation.
5. It can take up to 64K cycles for the PLL to lock after it has been enabled.
6. Special Loopback Modes are available in these devices to perform Address /
Control Input Training; they are selected and enabled via the Loopback Mode
Select (LBK[1:0]) and Loopback Mode Enable (LBKE) bits in the Configuration
Registers.
7. If Loopback Modes are used to perform Address / Control Input Training, then
Register Write Mode will likely have to be utilized in the “Asynchronous,
Pre-Input Training” method in order to change the states of the LBK[1:0] and
LBKE register bits.
8. Loopback Modes can also be used for Read Data Output Training, if desired.
See the Signal Timing Training and Loopback Mode sections for more informa-
tion.
9. “Additional Configuration” includes any other configuration changes required by
the system. Since this step is performed after Address / Control Input Training,
Register Write Mode can be utilized in the “Asynchronous, Post-Input Training”
method (or perhaps the “Synchronous” method, if the synchronous timing
requirements can be met at the particular operating frequency).
10. It is up to the system to determine if/when re-training is necessary.
Rev: 1.09 5/2016
6/40
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2014, GSI Technology

6 Page



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部品番号部品説明メーカ
GS81314LQ36GK

144Mb SigmaQuad-IVe Burst of 2 Multi-Bank ECCRAM

GSI Technology
GSI Technology


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