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GS81313LD18GK の電気的特性と機能

GS81313LD18GKのメーカーはGSI Technologyです、この部品の機能は「144Mb SigmaQuad-IIIe Burst of 4 ECCRAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 GS81313LD18GK
部品説明 144Mb SigmaQuad-IIIe Burst of 4 ECCRAM
メーカ GSI Technology
ロゴ GSI Technology ロゴ 




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GS81313LD18GK Datasheet, GS81313LD18GK PDF,ピン配置, 機能
GS81313LD18/36GK-833/714/625
260-Pin BGA
Com & Ind Temp
HSTL I/O
144Mb SigmaQuad-IIIe™
Burst of 4 ECCRAM™
Up to 833 MHz
1.25V ~ 1.3V VDD
1.2V ~ 1.3V VDDQ
Features
• 4Mb x 36 and 8Mb x 18 organizations available
• 833 MHz maximum operating frequency
• 833 MT/s peak transaction rate (in millions per second)
• 120 Gb/s peak data bandwidth (in x36 devices)
• Separate I/O DDR Data Buses
• Non-multiplexed SDR Address Bus
• One operation - Read or Write - per clock cycle
• Burst of 4 Read and Write operations
• 3 cycle Read Latency
• On-chip ECC with virtually zero SER
• 1.25V ~ 1.3V core voltage
• 1.2V ~ 1.3V HSTL I/O interface
• Configurable ODT (on-die termination)
• ZQ pin for programmable driver impedance
• ZT pin for programmable ODT impedance
• IEEE 1149.1 JTAG-compliant Boundary Scan
• 260-pin, 14 mm x 22 mm, 1 mm ball pitch, 6/6 RoHS-
compliant BGA package
SigmaQuad-IIIeFamily Overview
SigmaQuad-IIIe ECCRAMs are the Separate I/O half of the
SigmaQuad-IIIe/SigmaDDR-IIIe family of high performance
ECCRAMs. Although very similar to GSI's second generation
of networking SRAMs (the SigmaQuad-II/SigmaDDR-II
family), these third generation devices offer several new
features that help enable significantly higher performance.
Clocking and Addressing Schemes
The GS81313LD18/36GK SigmaQuad-IIIe ECCRAMs are
synchronous devices. They employ three pairs of positive and
negative input clocks; one pair of master clocks, CK and CK,
and two pairs of write data clocks, KD[1:0] and KD[1:0]. All
six input clocks are single-ended; that is, each is received by a
dedicated input buffer.
CK and CK are used to latch address and control inputs, and to
control all output timing. KD[1:0] and KD[1:0] are used solely
to latch data inputs.
Each internal read and write operation in a SigmaQuad-IIIe B4
ECCRAM is four times wider than the device I/O bus. An
input data bus de-multiplexer is used to accumulate incoming
data before it is simultaneously written to the memory array.
An output data multiplexer is used to capture the data produced
from a single memory array read and then route it to the
appropriate output drivers as needed. Therefore, the address
field of a SigmaQuad-IIIe B4 ECCRAM is always two address
pins less than the advertised index depth (e.g. the 8M x 18 has
2M addressable index).
On-Chip Error Correction Code
GSI's ECCRAMs implement an ECC algorithm that detects
and corrects all single-bit memory errors, including those
induced by SER events such as cosmic rays, alpha particles,
etc. The resulting Soft Error Rate of these devices is
anticipated to be <0.002 FITs/Mb — a 5-order-of-magnitude
improvement over comparable SRAMs with no on-chip ECC,
which typically have an SER of 200 FITs/Mb or more.
All quoted SER values are at sea level in New York City.
Speed Grade
-833
-714
-625
Parameter Synopsis
Max Operating Frequency
833 MHz
714 MHz
625 MHz
Read Latency
3 cycles
3 cycles
3 cycles
VDD
1.2V to 1.35V
1.2V to 1.35V
1.2V to 1.35V
Rev: 1.13 7/2016
1/26
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2014, GSI Technology

1 Page





GS81313LD18GK pdf, ピン配列
GS81313LD18/36GK-833/714/625
4M x 36 Pinout (Top View)
1 2 3 4 5 6 7 8 9 10 11 12 13
A
VDD
VDDQ
VDD
VDDQ
NC
(RSVD)
MCL
(CFG)
MCL
ZQ
PZT1 VDDQ VDD VDDQ VDD
B
VSS
Q35
VSS
D35
MCL
MCH
(B4M)
NC
(RSVD)
MCH
(SIOM)
PZT0
D0
VSS Q0
VSS
C Q26 VDDQ D26 VDDQ VSS SA VDD SA VSS VDDQ D9 VDDQ Q9
D
VSS Q34 VSS
D34
SA
VDDQ
NC
(288 Mb)
VDDQ
SA
D1
VSS Q1
VSS
E Q25 VDDQ D25 VDD VSS SA VSS SA VSS VDD D10 VDDQ Q10
F VSS Q33 VSS D33 SA VDD VDDQ VDD SA D2 VSS Q2 VSS
G Q24 Q32 D24 D32 VSS SA MZT1 SA VSS D3 D11 Q3 Q11
H Q23 VDDQ D23 VDDQ SA VDDQ W VDDQ SA VDDQ D12 VDDQ Q12
J VSS Q31 VSS D31 VSS SA VSS SA VSS D4 VSS Q4 VSS
K CQ1 VDDQ VREF VDD KD1 VDD CK VDD KD0 VDD VREF VDDQ CQ0
L CQ1 VSS QVLD1 VSS KD1 VDDQ CK VDDQ KD0 VSS QVLD0 VSS CQ0
M VSS Q22 VSS D22 VSS SA VSS SA VSS D13 VSS Q13 VSS
N Q30 VDDQ D30 VDDQ PLL VDDQ R VDDQ MCH VDDQ D5 VDDQ Q5
P Q29 Q21 D29 D21 VSS SA MZT0 SA VSS D14 D6 Q14 Q6
R VSS Q20 VSS D20 MCH VDD VDDQ VDD RST D15 VSS Q15 VSS
T Q28 VDDQ D28 VDD VSS SA VSS SA VSS VDD D7 VDDQ Q7
U
VSS
Q19
VSS
D19
NC
(576 Mb)
VDDQ
NC
(RSVD)
VDDQ
NC
(1152 Mb)
D16
VSS
Q16
VSS
V
Q27 VDDQ D27 VDDQ VSS
NUI
(x18)
VDD
NUI
(B2)
VSS VDDQ D8 VDDQ Q8
W VSS Q18 VSS D18 TCK MCL RCS MCL TMS D17 VSS Q17 VSS
Y
VDD VDDQ VDD VDDQ TDO
ZT
NC
(RSVD)
MCL
TDI
VDDQ VDD VDDQ VDD
Notes:
1. Pins 5B, 6W, 7A, 8W, and 8Y must be tied Low in this device.
2. Pins 5R and 9N must be tied High in this device.
3. Pin 6A is defined as mode pin CFG in the pinout standard. It must be tied Low in this device to select x36 configuration.
4. Pin 8B is defined as mode pin SIOM in the pinout standard. It must be tied High in this device to select Separate I/O configuration.
5. Pin 6B is defined as mode pin B4M in the pinout standard. It must be tied High in this device to select Burst-of-4 configuration.
6. Pin 6V is defined as address pin SA for x18 devices. It is unused in this device, and must be left unconnected or driven Low.
7. Pin 8V is defined as address pin SA for B2 devices. It is unused in this device, and must be left unconnected or driven Low.
8. Pin 7D is reserved as address pin SA for 288 Mb devices. It is a true no connect in this device.
9. Pin 5U is reserved as address pin SA for 576 Mb devices. It is a true no connect in this device.
10. Pin 9U is reserved as address pin SA for 1152 Mb devices. It is a true no connect in this device.
Rev: 1.13 7/2016
3/26
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2014, GSI Technology


3Pages


GS81313LD18GK 電子部品, 半導体
GS81313LD18/36GK-833/714/625
Power-Up and Reset Requirements
For reliability purposes, power supplies must power up simultaneously, or in the following sequence:
VSS, VDD, VDDQ, VREF and inputs.
Power supplies must power down simultaneously, or in the reverse sequence.
After power supplies power up, the following start-up sequence must be followed.
Step 1 (Recommended, but not required): Assert RST High for at least 1ms.
While RST is asserted high:
• The PLL is disabled.
• The states of R, and W control inputs are ignored.
Note: If possible, RST should be asserted High before input clocks begin toggling, and remain asserted High until input clocks are
stable and toggling within specification, in order to prevent unstable, out-of-spec input clocks from causing trouble in the SRAM.
Step 2: Begin toggling input clocks.
After input clocks begin toggling, but not necessarily within specification:
• Q are placed in the non-Read state, and remain so until the first Read operation.
• QVLD are driven Low, and remain so until the first Read operation.
• CQ, CQ begin toggling, but not necessarily within specification.
Step 3: Wait until input clocks are stable and toggling within specification.
Step 4: De-assert RST Low (if asserted High).
Step 5: Wait at least 224K (229,376) cycles.
During this time:
• Driver and ODT impedances are calibrated. Can take up to 160K cycles.
• The current source for the PLL is calibrated (based on RCS pin). Can take up to 64K cycles.
Note: The PLL pin may be asserted High or de-asserted Low during this time. If asserted High, PLL synchronization begins
immediately after the current source for the PLL is calibrated. If de-asserted Low, PLL synchronization begins after the PLL pin is
asserted High (see Step 6). In either case, Step 7 must follow thereafter.
Step 6: Assert PLL pin High (if de-asserted Low).
Step 7: Wait at least 64K (65,536) cycles for the PLL to lock.
After the PLL has locked:
• CQ, CQ begin toggling within specification.
Step 8: Begin initiating Read and Write operations.
Reset Usage
Although not generally recommended, RST may be asserted High at any time after completion of the initial power-up sequence
described above, to reset the SRAM control logic to its initial power-on state. However, whenever RST is subsequently de-asserted
Low (as in Step 4 above), Steps 5~7 above must be followed before Read and Write operations are initiated.
Note: Memory array content may be perturbed/corrupted when RST is asserted High.
Rev: 1.13 7/2016
6/26
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2014, GSI Technology

6 Page



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部品番号部品説明メーカ
GS81313LD18GK

144Mb SigmaQuad-IIIe Burst of 4 ECCRAM

GSI Technology
GSI Technology


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