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GS81302Q37GEのメーカーはGSI Technologyです、この部品の機能は「144Mb SigmaQuad-II+ Burst of 2 SRAM」です。 |
部品番号 | GS81302Q37GE |
| |
部品説明 | 144Mb SigmaQuad-II+ Burst of 2 SRAM | ||
メーカ | GSI Technology | ||
ロゴ | |||
このページの下部にプレビューとGS81302Q37GEダウンロード(pdfファイル)リンクがあります。 Total 28 pages
GS81302Q07/10/19/37E-318/300/250/200
165-Bump BGA
Commercial Temp
Industrial Temp
144Mb SigmaQuad-II+TM
Burst of 2 SRAM
318 MHz–200 MHz
1.8 V VDD
1.8 V and 1.5 V I/O
Features
• 2.0 clock Latency
• Simultaneous Read and Write SigmaQuad™ Interface
• JEDEC-standard pinout and package
• Dual Double Data Rate interface
• Byte Write controls sampled at data-in time
• On-Die Termination (ODT) on Data (D), Byte Write (BW),
and Clock (K, K) inputs
• Burst of 2 Read and Write
• 1.8 V +100/–100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
• Pipelined read operation
• Fully coherent read and write pipelines
• ZQ pin for programmable output drive strength
• Data Valid Pin (QVLD) Support
• IEEE 1149.1 JTAG-compliant Boundary Scan
• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package
• RoHS-compliant 165-bump BGA package available
SigmaQuad™ Family Overview
The GS81302Q07/10/19/37E are built in compliance with the
SigmaQuad-II+ SRAM pinout standard for Separate I/O
synchronous SRAMs. They are 150,994,944-bit (144Mb)
SRAMs. The GS81302Q07/10/19/37E SigmaQuad SRAMs
are just one element in a family of low power, low voltage
HSTL I/O SRAMs designed to operate at the speeds needed to
implement economical high performance networking systems.
Clocking and Addressing Schemes
The GS81302Q07/10/19/37E SigmaQuad-II+ SRAMs are
synchronous devices. They employ two input register clock
inputs, K and K. K and K are independent single-ended clock
inputs, not differential inputs to a single differential clock input
buffer.
Each internal read and write operation in a SigmaQuad-II+ B2
RAM is two times wider than the device I/O bus. An input data
bus de-multiplexer is used to accumulate incoming data before
it is simultaneously written to the memory array. An output
data multiplexer is used to capture the data produced from a
single memory array read and then route it to the appropriate
output drivers as needed. Therefore the address field of a
SigmaQuad-II+ B2 RAM is always one address pin less than
the advertised index depth (e.g., the 16M x 8 has an 8M
addressable index).
Parameter Synopsis
tKHKH
tKHQV
-318
3.145 ns
0.45 ns
-300
3.3 ns
0.45 ns
-250
4.0 ns
0.45 ns
-200
5.0 ns
0.45 ns
Rev: 1.02e 5/2012
1/28
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2010, GSI Technology
1 Page GS81302Q07/10/19/37E-318/300/250/200
16M x 9 SigmaQuad-II SRAM—Top View
123456789
A CQ SA SA W NC K SA R SA
B
NC
NC
NC
SA
NC/SA
(288Mb)
K
BW0 SA
NC
C NC NC NC VSS SA SA SA VSS NC
D NC D5 NC VSS VSS VSS VSS VSS NC
E
NC
NC
Q5
VDDQ
VSS
VSS
VSS VDDQ NC
F
NC
NC
NC
VDDQ
VDD
VSS
VDD VDDQ NC
G
NC D6
Q6
VDDQ
VDD
VSS
VDD VDDQ NC
H
Doff
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
J
NC
NC
NC
VDDQ
VDD
VSS
VDD VDDQ NC
K
NC
NC
NC
VDDQ
VDD
VSS
VDD VDDQ NC
L
NC
Q7
D7
VDDQ
VSS
VSS
VSS VDDQ
NC
M NC NC NC VSS VSS VSS VSS VSS NC
N NC D8 NC VSS SA SA SA VSS NC
P NC NC Q8 SA SA QVLD SA SA NC
R TDO TCK
Notes:
1. BW0 controls writes to D0:D8.
2. B5 is the expansion address.
SA SA SA ODT SA SA SA
11 x 15 Bump BGA—15 x 17 mm Body—1 mm Bump Pitch
10
SA
NC
NC
NC
D3
NC
NC
VREF
Q2
NC
NC
NC
NC
D0
TMS
11
CQ
Q4
D4
NC
Q3
NC
NC
ZQ
D2
NC
Q1
D1
NC
Q0
TDI
Rev: 1.02e 5/2012
3/28
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2010, GSI Technology
3Pages GS81302Q07/10/19/37E-318/300/250/200
Pin Description Table
Symbol
Description
Type Comments
SA
Synchronous Address Inputs
Input —
R
Synchronous Read
Input Active Low
W
Synchronous Write
Input Active Low
BW0–BW3
Synchronous Byte Writes
Input Active Low
NW0–NW1
Synchronous Nybble Writes
Input
Active Low
(x8 only)
K
Input Clock
Input Active High
K
Input Clock
Input Active Low
TMS
Test Mode Select
Input —
TDI
Test Data Input
Input —
TCK
Test Clock Input
Input —
TDO
Test Data Output
Output
—
VREF
HSTL Input Reference Voltage
Input —
ZQ
Output Impedance Matching Input
Input
—
Qn
Synchronous Data Outputs
Output
—
Dn
Synchronous Data Inputs
Input —
Doff
Disable DLL when low
Input Active Low
CQ
Output Echo Clock
Output
—
CQ
Output Echo Clock
Output
—
VDD
Power Supply
Supply
1.8 V Nominal
VDDQ
Isolated Output Buffer Supply
Supply
1.8 V or 1.5 V Nominal
VSS
Power Supply: Ground
Supply
—
QVLD
Q Valid Output
Output
—
ODT
On-Die Termination
Input Active High
NC
No Connect
——
Notes:
1. NC = Not Connected to die or any other pin
2. When ZQ pin is directly connected to VDDQ, output impedance is set to minimum value and it cannot be connected to ground or left
unconnected.
3. K and K cannot be set to VREF voltage.
Rev: 1.02e 5/2012
6/28
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2010, GSI Technology
6 Page | |||
ページ | 合計 : 28 ページ | ||
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部品番号 | 部品説明 | メーカ |
GS81302Q37GE | 144Mb SigmaQuad-II+ Burst of 2 SRAM | GSI Technology |