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GS81302TT07GE の電気的特性と機能

GS81302TT07GEのメーカーはGSI Technologyです、この部品の機能は「144Mb SigmaDDR-II+ Burst of 2 SRAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 GS81302TT07GE
部品説明 144Mb SigmaDDR-II+ Burst of 2 SRAM
メーカ GSI Technology
ロゴ GSI Technology ロゴ 




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GS81302TT07GE Datasheet, GS81302TT07GE PDF,ピン配置, 機能
GS81302TT07/10/19/37E-450/400/350/333/300
165-Bump BGA
Commercial Temp
Industrial Temp
144Mb SigmaDDRTM-II+
Burst of 2 SRAM
450 MHz–300 MHz
1.8 V VDD
1.8 V or 1.5 V I/O
Features
• 2.0 Clock Latency
• Simultaneous Read and Write SigmaDDR™ Interface
• Common I/O bus
• JEDEC-standard pinout and package
• Double Data Rate interface
• Byte Write controls sampled at data-in time
• Burst of 2 Read and Write
• Dual-Range On-Die Termination (ODT) on Data (D), Byte
Write (BW), and Clock (K, K) inputs
• 1.8 V +100/–100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
• Pipelined read operation with self-timed Late Write
• Fully coherent read and write pipelines
• ZQ pin for programmable output drive strength
• Data Valid pin (QVLD) Support
• IEEE 1149.1 JTAG-compliant Boundary Scan
• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package
• RoHS-compliant 165-bump BGA package available
SigmaDDRFamily Overview
The GS81302TT07/10/19/37E are built in compliance with the
SigmaDDR-II+ SRAM pinout standard for Common I/O
synchronous SRAMs. They are 150,994,944-bit (144Mb)
SRAMs. The GS81302TT07/10/19/37E SigmaDDR-II+
SRAMs are just one element in a family of low power, low
voltage HSTL I/O SRAMs designed to operate at the speeds
needed to implement economical high performance
networking systems.
Clocking and Addressing Schemes
The GS81302TT07/10/19/37E SigmaDDR-II+ SRAMs are
synchronous devices. They employ two input register clock
inputs, K and K. K and K are independent single-ended clock
inputs, not differential inputs to a single differential clock input
buffer.
Each internal read and write operation in a SigmaDDR-II+ B2
RAM is two times wider than the device I/O bus. An input data
bus de-multiplexer is used to accumulate incoming data before
it is simultaneously written to the memory array. An output
data multiplexer is used to capture the data produced from a
single memory array read and then route it to the appropriate
output drivers as needed. Therefore, the address field of a
SigmaDDR-II+ B2 RAM is always one address pin less than
the advertised index depth (e.g., the 16M x 8 has an 8M
addressable index).
Parameter Synopsis
tKHKH
tKHQV
-450
2.2 ns
0.45 ns
-400
2.5 ns
0.45 ns
-350
2.86 ns
0.45 ns
-333
3.0 ns
0.45 ns
-300
3.3 ns
0.45 ns
Rev: 1.00a 11/2011
1/30
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology

1 Page





GS81302TT07GE pdf, ピン配列
GS81302TT07/10/19/37E-450/400/350/333/300
16M x 9 SigmaDDR-II+ SRAM—Top View
123456789
A CQ SA SA R/W NC K SA LD SA
B
NC
NC
NC
SA
NC/SA
(288Mb)
K
BW0 SA
NC
C NC NC NC VSS SA SA SA VSS NC
D NC NC NC VSS VSS VSS VSS VSS NC
E NC NC DQ5 VDDQ VSS VSS VSS VDDQ NC
F
NC
NC
NC
VDDQ
VDD
VSS
VDD VDDQ NC
G NC NC DQ6 VDDQ VDD VSS VDD VDDQ NC
H
Doff
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
J
NC
NC
NC
VDDQ
VDD
VSS
VDD VDDQ NC
K
NC
NC
NC
VDDQ
VDD
VSS
VDD VDDQ NC
L
NC
DQ7
NC
VDDQ
VSS
VSS
VSS VDDQ NC
M NC NC NC VSS VSS VSS VSS VSS NC
N NC NC NC VSS SA SA SA VSS NC
P NC NC DQ8 SA SA QVLD SA SA NC
R
TDO TCK
SA
SA
SA ODT SA
SA
SA
Notes:
3. BW0 controls writes to DQ0 :DQ8.
4. Pin B5 is the expansion address.
11 x 15 Bump BGA—15 x 17 mm2 Body—1 mm Bump Pitch
10
SA
NC
NC
NC
NC
NC
NC
VREF
DQ2
NC
NC
NC
NC
NC
TMS
11
CQ
DQ4
NC
NC
DQ3
NC
NC
ZQ
NC
NC
DQ1
NC
NC
DQ0
TDI
Rev: 1.00a 11/2011
3/30
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology


3Pages


GS81302TT07GE 電子部品, 半導体
GS81302TT07/10/19/37E-450/400/350/333/300
Pin Description Table
Symbol
Description
Type Comments
SA
Synchronous Address Inputs
Input —
R/W
Synchronous Read
Input
High: Read
Low: Write
BW0–BW3
Synchronous Byte Writes
Input Active Low
LD
Synchronous Load Pin
Input Active Low
K
Input Clock
Input Active High
K
Input Clock
Input Active Low
TMS
Test Mode Select
Input —
TDI
Test Data Input
Input —
TCK
Test Clock Input
Input —
TDO
Test Data Output
Output
VREF
HSTL Input Reference Voltage
Input —
ZQ
Output Impedance Matching Input
Input
MCL
Must Connect Low
——
DQ
Data I/O
Input/Output
Three State
Doff
Disable DLL when low
Input Active Low
CQ
Output Echo Clock
Output
CQ
Output Echo Clock
Output
VDD
Power Supply
Supply
1.8 V Nominal
VDDQ
Isolated Output Buffer Supply
Supply
1.8 V or 1.5 V Nominal
VSS
Power Supply: Ground
Supply
QVLD
Q Valid Output
Output
ODT
On-Die Termination
Input
Low = Low Impedance Range
High/Float = High Impedance Range
NC
No Connect
——
Notes:
1. NC = Not Connected to die or any other pin
2. When ZQ pin is directly connected to VDDQ, output impedance is set to minimum value and it cannot be connected to ground or left
unconnected.
3. K and K cannot be set to VREF voltage.
Rev: 1.00a 11/2011
6/30
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology

6 Page



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部品番号部品説明メーカ
GS81302TT07GE

144Mb SigmaDDR-II+ Burst of 2 SRAM

GSI Technology
GSI Technology


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