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GS81302D06E-350 の電気的特性と機能

GS81302D06E-350のメーカーはGSI Technologyです、この部品の機能は「144Mb SigmaQuad-II+ Burst of 4 SRAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 GS81302D06E-350
部品説明 144Mb SigmaQuad-II+ Burst of 4 SRAM
メーカ GSI Technology
ロゴ GSI Technology ロゴ 




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GS81302D06E-350 Datasheet, GS81302D06E-350 PDF,ピン配置, 機能
GS81302D06/11/20/38E-500/450/400/350
165-Bump BGA
Commercial Temp
Industrial Temp
144Mb SigmaQuad-II+
Burst of 4 SRAM
500 MHz–350 MHz
1.8 V VDD
1.8 V or 1.5 V I/O
Features
• 2.5 Clock Latency
• Simultaneous Read and Write SigmaQuad™ Interface
• JEDEC-standard pinout and package
• Dual Double Data Rate interface
• Byte Write controls sampled at data-in time
• Burst of 4 Read and Write
• On-Die Termination (ODT) on Data (D), Byte Write (BW),
and Clock (K, K) intputs
• 1.8 V +100/–100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
• Pipelined read operation
• Fully coherent read and write pipelines
• ZQ pin for programmable output drive strength
• Data Valid Pin (QVLD) Support
• IEEE 1149.1 JTAG-compliant Boundary Scan
• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package
• RoHS-compliant 165-bump BGA package available
SigmaQuadFamily Overview
The GS81302D06/11/20/38E are built in compliance with the
SigmaQuad-II+ SRAM pinout standard for Separate I/O
synchronous SRAMs. They are 150,994,944-bit (144Mb)
SRAMs. The GS81302D06/11/20/38E SigmaQuad SRAMs
are just one element in a family of low power, low voltage
HSTL I/O SRAMs designed to operate at the speeds needed to
implement economical high performance networking systems.
Clocking and Addressing Schemes
The GS81302D06/11/20/38E SigmaQuad-II+ SRAMs are
synchronous devices. They employ two input register clock
inputs, K and K. K and K are independent single-ended clock
inputs, not differential inputs to a single differential clock input
buffer.
Each internal read and write operation in a SigmaQuad-II+ B4
RAM is four times wider than the device I/O bus. An input
data bus de-multiplexer is used to accumulate incoming data
before it is simultaneously written to the memory array. An
output data multiplexer is used to capture the data produced
from a single memory array read and then route it to the
appropriate output drivers as needed. Therefore the address
field of a SigmaQuad-II+ B4 RAM is always two address pins
less than the advertised index depth (e.g., the 16M x 8 has a
4M addressable index).
tKHKH
tKHQV
Parameter Synopsis
-500
2.0 ns
0.45 ns
-450
2.2 ns
0.45 ns
-400
2.5 ns
0.45 ns
-350
2.86 ns
0.45 ns
Rev: 1.05b 6/2014
1/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology

1 Page





GS81302D06E-350 pdf, ピン配列
GS81302D06/11/20/38E-500/450/400/350
8M x 18 SigmaQuad-II+ SRAM—Top View
123456789
A
CQ SA SA
W
BW1
K
NC/SA
(288Mb)
R
SA
B NC Q9 D9 SA NC K BW0 SA NC
C NC NC D10 VSS SA NC SA VSS NC
D NC D11 Q10 VSS VSS VSS VSS VSS NC
E NC NC Q11 VDDQ VSS VSS VSS VDDQ NC
F
NC
Q12
D12
VDDQ
VDD
VSS
VDD VDDQ NC
G
NC
D13
Q13
VDDQ
VDD
VSS
VDD VDDQ NC
H
Doff
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
J
NC
NC
D14
VDDQ
VDD
VSS
VDD VDDQ NC
K NC NC Q14 VDDQ VDD VSS VDD VDDQ NC
L NC Q15 D15 VDDQ VSS VSS VSS VDDQ NC
M NC NC D16 VSS VSS VSS VSS VSS NC
N NC D17 Q16 VSS SA SA SA VSS NC
P NC NC Q17 SA SA QVLD SA SA NC
R
TDO TCK
SA
SA
SA ODT SA
SA
SA
11 x 15 Bump BGA—15 x 17 mm2 Body—1 mm Bump Pitch
Notes:
1. BW0 controls writes to D0:D8. BW1 controls writes to D9:D17.
2. Pin A7 is the expansion address.
10
SA
NC
Q7
NC
D6
NC
NC
VREF
Q4
D3
NC
Q1
NC
D0
TMS
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
Rev: 1.05b 6/2014
3/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology


3Pages


GS81302D06E-350 電子部品, 半導体
GS81302D06/11/20/38E-500/450/400/350
Pin Description Table
Symbol
Description
Type Comments
SA
Synchronous Address Inputs
Input —
R
Synchronous Read
Input Active Low
W
Synchronous Write
Input Active Low
BW0–BW3
Synchronous Byte Writes
Input
Active Low
x18/x36 only
K
Input Clock
Input Active High
K
Input Clock
Input Active Low
TMS
Test Mode Select
Input —
TDI
Test Data Input
Input —
TCK
Test Clock Input
Input —
TDO
Test Data Output
Output
VREF
HSTL Input Reference Voltage
Input —
ZQ
Output Impedance Matching Input
Input
Qn
Synchronous Data Outputs
Output
Dn
Synchronous Data Inputs
Input —
Doff
Disable DLL when low
Input Active Low
CQ
Output Echo Clock
Output
CQ
Output Echo Clock
Output
VDD
Power Supply
Supply
1.8 V Nominal
VDDQ
Isolated Output Buffer Supply
Supply
1.5 V or 1.8 V Nominal
VSS
Power Supply: Ground
Supply
QVLD
Q Valid Output
Output
ODT
On-Die Termination
Input Active High
NC
No Connect
——
Notes:
1. NC = Not Connected to die or any other pin
2. When ZQ pin is directly connected to VDDQ, output impedance is set to minimum value and it cannot be connected to ground or left
unconnected.
3. K and K cannot be set to VREF voltage.
Rev: 1.05b 6/2014
6/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology

6 Page



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共有リンク

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部品番号部品説明メーカ
GS81302D06E-350

144Mb SigmaQuad-II+ Burst of 4 SRAM

GSI Technology
GSI Technology
GS81302D06E-350I

144Mb SigmaQuad-II+ Burst of 4 SRAM

GSI Technology
GSI Technology


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