DataSheet.jp

GS9091B の電気的特性と機能

GS9091BのメーカーはGennumです、この部品の機能は「270Mb/s Deserializer」です。


製品の詳細 ( Datasheet PDF )

部品番号 GS9091B
部品説明 270Mb/s Deserializer
メーカ Gennum
ロゴ Gennum ロゴ 




このページの下部にプレビューとGS9091Bダウンロード(pdfファイル)リンクがあります。

Total 30 pages

No Preview Available !

GS9091B Datasheet, GS9091B PDF,ピン配置, 機能
GS9091B GenLINX® II 270Mb/s Deserializer for SDI and DVB-ASI
Key Features
• SMPTE 259M-C compliant descrambling and NRZI to
NRZ decoding (with bypass)
• DVB-ASI 8b/10b decoding
• Integrated Cable Equalizer
• 500m typical equalization of Belden 1694A cable
• Integrated line-based FIFO for data alignment/delay,
clock phase interchange, DVB-ASI data packet
extraction and clock rate interchange, and ancillary
data packet extraction
• Integrated VCO and reclocker
• User selectable additional processing features
including:
Š TRS, ANC data checksum, and EDH CRC error
detection and correction
Š programmable ANC data detection
Š illegal code remapping
• Internal flywheel for noise immune H, V, F extraction
• Automatic standards detection and indication
• Enhanced Gennum Serial Peripheral Interface (GSPI)
• JTAG test interface
• Polarity insensitive for DVB-ASI and SMPTE signals
• +1.8V core power supply with optional +1.8V or +3.3V
I/O power supply
• Small footprint (11mm x 11mm)
• Low power operation (typically 350mW)
• Pb-free and RoHS compliant
Applications
• SMPTE 259M-C Serial Digital Interfaces
• DVB-ASI Serial Digital Interfaces
Description
The GS9091B is a 270Mb/s equalizing and reclocking dese-
rializer with an internal FIFO. It provides a complete re-
ceive solution for SD-SDI and DVB-ASI applications.
In addition to equalizing, reclocking and deserializing the
input data stream, the GS9091B performs NRZI -to-NRZ de-
coding, descrambling as per SMPTE 259M-C, and word
alignment when operating in SMPTE mode. When operat-
ing in DVB-ASI mode, the device will word align the data to
K28.5 sync characters and 8b/10b decode the received
stream.
The integrated equalizer is optimized for 270Mb/s and can
typically equalize up to 500m of Belden 1694A cable. Both
the equalizer and the internal reclocker are fully compati-
ble with both SMPTE and DVB-ASI input streams.
The GS9091B includes a range of data processing functions
such as EDH support (error detection and handling), and
automatic standards detection. The device can also detect
and extract SMPTE 352M payload identifier packets and in-
dependently identify the received video standard. This in-
formation is read from internal registers via the host
interface port.
The GS9091B also incorporates a video line-based FIFO.
This FIFO may be used in four user-selectable modes to car-
ry out tasks such as data alignment / delay, clock phase in-
terchange, MPEG packet extraction and clock rate
interchange, and ancillary data packet extraction.
Parallel data outputs are provided in 10-bit multiplexed
format, with the associated parallel clock output signal op-
erating at 27MHz.
The device may also be used in a low-latency data pass
through mode where only descrambling and word align-
ment will be performed in SMPTE mode.
GS9091B GenLINX® II 270Mb/s Deserializer for SDI and DVB-ASI www.gennum.com
Data Sheet
38910 - 2
July 2008
1 of 71
Proprietary & Confidential

1 Page





GS9091B pdf, ピン配列
Revision History
Version ECR
PCN
0 139930
1 144807
2 150199 50711
Date
Changes and/or Modifications
November 2006
April 2007
July 2008
New Document.
Converting to Data Sheet. Modified Electrical Characteristics.
DVB_ASI operation specification change in Auto mode.
Contents
Key Features ........................................................................................................................................................1
Applications ......................................................................................................................................................... 1
Description ........................................................................................................................................................... 1
Functional Block Diagram ..............................................................................................................................2
1. Pin Out...............................................................................................................................................................5
1.1 Pin Assignment...................................................................................................................................5
2. Electrical Characteristics ......................................................................................................................... 12
2.1 DC Electrical Characteristics ...................................................................................................... 12
2.2 AC Electrical Characteristics ...................................................................................................... 14
2.3 Solder Reflow Profiles................................................................................................................... 16
2.4 Host Interface Map......................................................................................................................... 17
2.4.1 Host Interface Map (R/W registers) ............................................................................. 19
2.4.2 Host Interface Map (Read only registers) .................................................................. 21
3. Detailed Description.................................................................................................................................. 23
3.1 Functional Overview..................................................................................................................... 23
3.2 Cable Equalization ......................................................................................................................... 24
3.3 Clock and Data Recovery............................................................................................................. 24
3.3.1 Internal VCO and Phase Detector................................................................................ 24
3.4 Serial-To-Parallel Conversion .................................................................................................... 24
3.5 Modes Of Operation ...................................................................................................................... 24
3.5.1 Lock Detect .......................................................................................................................... 25
3.5.2 Auto Mode............................................................................................................................ 27
3.5.3 Manual Mode ...................................................................................................................... 27
3.6 SMPTE Functionality ..................................................................................................................... 28
3.6.1 SMPTE Descrambling and Word Alignment ............................................................ 28
3.6.2 Internal Flywheel .............................................................................................................. 28
3.6.3 Switch Line Lock Handling............................................................................................. 29
3.6.4 HVF Timing Signal Generation ..................................................................................... 30
3.7 DVB-ASI Functionality ................................................................................................................. 31
GS9091B GenLINX® II 270Mb/s Deserializer for SDI
and DVB-ASI
Data Sheet
38910 - 2
July 2008
3 of 71
Proprietary & Confidential


3Pages


GS9091B 電子部品, 半導体
Table 1-1: Ball List and Description
Ball Name
A1 LF+
A2, B5, C3,
C4, C5, C6,
C7, C9, D3,
D8, D9, E3,
E8, F8, G8,
G9, H4, H5,
H6, H7, K2
A3
NC
LB_CONT
A4 VCO_VDD
A5 VBG
A6 FIFO_EN
A7 AUTO/MAN
A8 LOCKED
A9 PCLK
Timing
Analog
Type
Input
Description
Loop filter component connection. Connect to LF- through a 4.4nF
capacitor.
No connect. Not connected internally.
Analog
Input
CONTROL SIGNAL INPUT
Control voltage to fine-tune the loop bandwidth of the PLL.
Analog
Input
Power
Power supply connection for Voltage-Controlled-Oscillator.
Connect to +1.8V DC.
Analog
Input
Bandgap filter capacitor. Connect to GND as shown in Typical
Application Circuit.
Non Input
Synchronous
CONTOL SIGNAL INPUT
Signal levels are LVCMOS / LVTTL compatible.
Used to enable / disable the internal FIFO.
When FIFO_EN is HIGH, the internal FIFO will be enabled. Data will
be clocked out of the device on the rising edge of the RD_CLK
input pin if the FIFO is in video mode or DVB-ASI mode.
When FIFO_EN is LOW, the internal FIFO is bypassed and parallel
data is clocked out on the rising edge of the PCLK output.
Non Input
Synchronous
CONTROL SIGNAL INPUT
Signal levels are LVCMOS / LVTTL compatible.
When set HIGH, the GS9091B will operate in Auto mode. The
SMPTE_BYPASS pin becomes an output status signal set by the
device. In this mode, the GS9091B will automatically detect,
reclock, deserialize, and process SMPTE compliant input data.
When set LOW, the GS9091B will operate in Manual mode. The
DVB_ASI and SMPTE_BYPASS pins become input control signals. In
this mode, the application layer must set these two external pins
for the correct reception of either SMPTE or DVB-ASI data. Manual
mode also supports the reclocking and deserializing of data not
conforming to SMPTE or DVB-ASI streams.
Synchronous
with PCLK
Output
STATUS SIGNAL OUTPUT
Signal levels are LVCMOS / LVTTL compatible.
The LOCKED pin will be HIGH whenever the device has correctly
received and locked to SMPTE compliant data in SMPTE mode or
DVB-ASI compliant data in DVB-ASI mode, or when the reclocker
has achieved lock in Data-Through mode.
It will be LOW otherwise. When the pin is LOW, all digital output
signals will be forced to logic LOW levels.
– Output PIXEL CLOCK OUTPUT
Signal levels are LVCMOS / LVTTL compatible.
27MHz parallel clock output.
GS9091B GenLINX® II 270Mb/s Deserializer for SDI
and DVB-ASI
Data Sheet
38910 - 2
July 2008
6 of 71
Proprietary & Confidential

6 Page



ページ 合計 : 30 ページ
 
PDF
ダウンロード
[ GS9091B データシート.PDF ]


データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。


共有リンク

Link :


部品番号部品説明メーカ
GS9091B

270Mb/s Deserializer

Semtech
Semtech
GS9091B

270Mb/s Deserializer

Gennum
Gennum


www.DataSheet.jp    |   2020   |  メール    |   最新    |   Sitemap