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54190 の電気的特性と機能

54190のメーカーはMotorola Semiconductorsです、この部品の機能は「PRESETTABLE 4-BIT BINARY UP/DOWN COUNTERS」です。


製品の詳細 ( Datasheet PDF )

部品番号 54190
部品説明 PRESETTABLE 4-BIT BINARY UP/DOWN COUNTERS
メーカ Motorola Semiconductors
ロゴ Motorola Semiconductors ロゴ 




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54190 Datasheet, 54190 PDF,ピン配置, 機能
PRESETTABLE BCD/DECADE
UP/DOWN COUNTERS
PRESETTABLE 4-BIT BINARY
UP/DOWN COUNTERS
The SN54 / 74LS190 is a synchronous UP/ DOWN BCD Decade (8421)
Counter and the SN54/ 74LS191 is a synchronous UP / DOWN Modulo-16
Binary Counter. State changes of the counters are synchronous with the
LOW-to-HIGH transition of the Clock Pulse input.
An asynchronous Parallel Load (PL) input overrides counting and loads the
data present on the Pn inputs into the flip-flops, which makes it possible to use
the circuits as programmable counters. A Count Enable (CE) input serves as
the carry / borrow input in multi-stage counters. An Up / Down Count Control
(U/D) input determines whether a circuit counts up or down. A Terminal Count
(TC) output and a Ripple Clock (RC) output provide overflow/underflow
indication and make possible a variety of methods for generating
carry / borrow signals in multistage counter applications.
Low Power . . . 90 mW Typical Dissipation
High Speed . . . 25 MHz Typical Count Frequency
Synchronous Counting
Asynchronous Parallel Load
Individual Preset Inputs
Count Enable and Up/ Down Control Inputs
Cascadable
Input Clamp Diodes Limit High Speed Termination Effects
CONNECTION DIAGRAM DIP (TOP VIEW)
VCC
16
P0
15
CP
14
RC
13
TC
12
PL
11
P2
10
P3
9
NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
1
P1
2
Q1
3
Q0
4
CE
5
U/D
6
Q2
7
Q3
8
GND
PIN NAMES
LOADING (Note a)
HIGH
LOW
CE Count Enable (Active LOW) Input
1.5 U.L.
0.7 U.L.
CP Clock Pulse (Active HIGH going edge) Input 0.5 U.L. 0.25 U.L.
U / D Up/Down Count Control Input
0.5 U.L.
0.25 U.L.
PL Parallel Load Control (Active LOW) Input
0.5 U.L.
0.25 U.L.
Pn Parallel Data Inputs
Qn Flip-Flop Outputs (Note b)
RC Ripple Clock Output (Note b)
0.5 U.L.
10 U.L.
10 U.L.
0.25 U.L.
5 (2.5) U.L.
5 (2.5) U.L.
TC Terminal Count Output (Note b)
10 U.L. 5 (2.5) U.L.
NOTES:
a. 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.
b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)
b. Temperature Ranges.
FAST AND LS TTL DATA
5-341
SN54/74LS190
SN54/74LS191
PRESETTABLE BCD/ DECADE
UP/ DOWN COUNTERS
PRESETTABLE 4-BIT BINARY
UP/ DOWN COUNTERS
LOW POWER SCHOTTKY
16
1
J SUFFIX
CERAMIC
CASE 620-09
16
1
N SUFFIX
PLASTIC
CASE 648-08
16
1
D SUFFIX
SOIC
CASE 751B-03
ORDERING INFORMATION
SN54LSXXXJ
SN74LSXXXN
SN74LSXXXD
Ceramic
Plastic
SOIC
LOGIC SYMBOL
11 15 1 10 9
5
4
14
PL
U/D
P0 P1 P2
P3
RC
CE
CP
Q0 Q1
TC
Q2 Q3
32 6 7
VCC = PIN 16
GND = PIN 8
13
12

1 Page





54190 pdf, ピン配列
SN54/74LS190 SN54/74LS191
LOGIC DIAGRAMS (continued)
CP U/D
14
5
P0
15
CE
4
P1
1
P2
10
P3
9
PL
11
13
12
RC
TC
VCC = PIN 16
GND = PIN 8
= PIN NUMBERS
J CLOCK K
PRESET CLEAR
QQ
3
Q0
J CLOCK K
PRESET CLEAR
QQ
2
Q1
J CLOCK K
PRESET CLEAR
QQ
6
Q2
BINARY COUNTER
LS191
J CLOCK K
PRESET CLEAR
QQ
7
Q3
FAST AND LS TTL DATA
5-343


3Pages


54190 電子部品, 半導体
SN54/74LS190 SN54/74LS191
AC CHARACTERISTICS (TA = 25°C)
Symbol
fMAX
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
Parameter
Maximum Clock Frequency
Propagation Delay,
PL to Output Q
Data to Output Q
Clock to RC
Clock to Output Q
Clock to TC
U / D to RC
U / D to TC
CE to RC
AC SETUP REQUIREMENTS (TA = 25°C)
Symbol
tW
tW
ts
th
trec
Parameter
CP Pulse Width
PL Pulse Width
Data Setup Time
Data Hold Time
Recovery Time
Limits
Min Typ Max
20 25
22 33
33 50
20 32
27 40
13 20
16 24
16 24
24 36
28 42
37 52
30 45
30 45
21 33
22 33
21 33
22 33
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
Limits
Min Typ Max
25
35
20
5.0
40
Unit
ns
ns
ns
ns
ns
Test Conditions
VCC = 5.0 V
CL = 15 pF
Test Conditions
VCC = 5.0 V
DEFINITIONS OF TERMS
SETUP TIME (ts) is defined as the minimum time required for
the correct logic level to be present at the logic input prior to the
clock transition from LOW-to-HIGH in order to be recognized
and transferred to the outputs.
HOLD TIME (th) is defined as the minimum time following the
clock transition from LOW-to-HIGH that the logic level must be
maintained at the input in order to ensure continued recogni-
tion. A negative HOLD TIME indicates that the correct logic
level may be released prior to the clock transition from LOW-
to-HIGH and still be recognized.
RECOVERY TIME (trec) is defined as the minimum time
required between the end of the reset pulse and the clock
transition from LOW-to-HIGH in order to recognize and
transfer HIGH data to the Q outputs.
FAST AND LS TTL DATA
5-346

6 Page



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共有リンク

Link :


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54190

Synchronous Decade Up/Down Counters

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54190

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54190

Synchronous Up/Down Counters With Down/Up Mode Control

Texas Instruments
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54190

PRESETTABLE 4-BIT BINARY UP/DOWN COUNTERS

Motorola Semiconductors
Motorola Semiconductors


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