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PDF ADM1260 Data sheet ( Hoja de datos )

Número de pieza ADM1260
Descripción Super Sequencer
Fabricantes Analog Devices 
Logotipo Analog Devices Logotipo



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Data Sheet
Super Sequencer with Interchip Bus and
Nonvolatile Fault Recording
ADM1260
FEATURES
Complete supervisory and sequencing solution for up to
10 supplies per device
Interchip bus (ICB) simplifies multidevice connections and
sequencing system operation
Supports up to 4 devices
16 event deep black box nonvolatile fault recording
10 supply fault detectors enable supervision of supplies
<0.5% accuracy at all voltages at 25°C
<1.0% accuracy across all voltages and temperatures
5 selectable input attenuators allow supervision of supplies
14.4 V on VH and 6.0 V on VP1 to VP4 (VPx)
5 dual function inputs: VX1 to VX5 (VXx)
High impedance input to supply fault detector with
thresholds between 0.573 V and 1.375 V
General-purpose logic input
10 programmable driver outputs: PDO1 to PDO10 (PDOx)
Open-collector with an external pull-up resistor
Push/pull output, driven to VDDCAP or VPx
Open-collector with weak pull-up to VDDCAP or VPx
Internally charge pumped high drive for use with external
N-FET (PDO1 to PDO6 only)
Sequencing engine (SE) implements state machine control of
the PDOx outputs
State changes conditional on input events
Enables complex control of boards
Power-up and power-down sequence control
Fault event handling
Interrupt generation on warnings
Watchdog function can be integrated in the SE
Program software control of sequencing through the SMBus
Complete voltage margining solution for 6 voltage rails
6 output voltage 8-bit DACs (0.300 V to 1.552 V) allow voltage
adjustment via dc-to-dc converter trim/feedback node
12-bit ADC for readback of all supervised voltages
Reference input (REFIN) with two input options
Driven directly from the 2.048 V (±0.25%) REFOUT pin
External reference for improved ADC performance
Powered by the highest voltage on either VPx or VH
Voltage on VPx or VH must be greater than the
undervoltage lockout (UVLO) threshold
Electronically erasable programmable read-only memory
(EEPROM)
Industry-standard, 2-wire bus interface (SMBus)
PDOx pins guaranteed low with VH and VPx = 1.2 V
Available in a 40-lead, 6 mm × 6 mm LFCSP package
FUNCTIONAL BLOCK DIAGRAM
REFOUT REFGND
REFIN CDA
CCL SDA SCL A1 A0
VX1
VX2
VX3
VX4
VX5
VP1
VP2
VP3
VP4
VH
AGND
VREF
ADM1260
INTERCHIP
BUS
12-BIT
SAR ADC
CLOSED-LOOP
MARGINING SYSTEM
DUAL-
FUNCTION
INPUTS
(LOGIC INPUTS
OR
SFDs)
SEQUENCING
ENGINE
PROGRAMMABLE
RESET
GENERATORS
(SFDs)
VOUT VOUT VOUT VOUT VOUT VOUT
DAC DAC DAC DAC DAC DAC
SMBus
INTERFACE
EEPROM
FAULT
RECORDING
CONFIGURABLE
OUTPUT
DRIVERS
(HV CAPABLE OF
DRIVING GATES
OF N-FET)
CONFIGURABLE
OUTPUT
DRIVERS
(LV CAPABLE
OF DRIVING
LOGIC SIGNALS)
VDD
ARBITRATOR
PDO1
PDO2
PDO3
PDO4
PDO5
PDO6
PDO7
PDO8
PDO9
PDO10
PDOGND
VDDCAP
DAC1 DAC2 DAC3 DAC4 DAC5 DAC6
Figure 1.
VCCP GND
APPLICATIONS
Central office systems
Servers/routers
Multivoltage system line cards
Digital signal processor (DSP)/field programmable gate
array (FPGA) supply sequencing
In-circuit testing of margined supplies
Rev. 0
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com

1 page




ADM1260 pdf
Data Sheet
ADM1260
SPECIFICATIONS
VH = 3.0 V to 14.4 V,1 VPx = 3.0 V to 6.0 V,1 TA = −40°C to +85°C, unless otherwise noted.
Table 1.
Parameter
POWER SUPPLY ARBITRATION
VH, VPx
VPx
VH
VDDCAP
CVDDCAP
POWER SUPPLY
Supply Current, IVH, IVPx
Additional Currents
All PDOx FET Drivers On
Min
3.0
2.7
10
Current Available from VDDCAP
DAC Supply Currents
ADC Supply Current
EEPROM Erase Current
SUPPLY FAULT DETECTORS
VH
Input Impedance
Input Attenuator Error
Detection Ranges
High Range
Midrange
VPx
Input Impedance
Input Attenuator Error
Detection Ranges
Midrange
Low Range
Ultralow Range
VXx
Input Impedance
Detection Range
Ultralow Range
Absolute Accuracy
6.0
2.5
2.5
1.25
0.573
1
0.573
Threshold Resolution
Digital Glitch Filter
Typ Max Unit
6.0
14.4
4.75 5.4
V
V
V
V
μF
4.5 6.5
mA
1
2
2.2
1
10
mA
mA
mA
mA
mA
52
±0.05
%
14.4 V
6.0 V
52
±0.05
%
6.0
3.00
1.375
V
V
V
1.375
±1
V
%
8 Bits
0 μs
100 μs
Test Conditions/Comments
Minimum supply required on one of VPx or VH pins
Maximum VDDCAP = 5.1 V, typical
VDDCAP = 4.75 V
Regulated low dropout (LDO) output
Minimum recommended decoupling capacitance
VDDCAP = 4.75 V, PDO1 to PDO10 off, DACs off, ADC off
VDDCAP = 4.75 V, PDO1 to PDO6 loaded with 1 μA each,
PDO7 to PDO10 off
Maximum additional load that can be drawn from all
PDO pull-ups to VDDCAP
Six DACs on with 100 μA maximum load on each
Running round robin loop
1 ms duration only, VDDCAP = 3 V
Midrange and high range
Low range and midrange
No input attenuation error
No input attenuation error
VREF error + DAC nonlinearity + comparator offset error +
input attenuation error (±0.5% at 25°C)
Minimum programmable filter length
Maximum programmable filter length
Rev. 0 | Page 5 of 71

5 Page





ADM1260 arduino
ADM1260
TYPICAL PERFORMANCE CHARACTERISTICS
6
5
4
3
2
1
0
0123456
VVP1 (V)
Figure 4. VVDDCAP vs. VVP1
6
5
4
3
2
1
0
0 2 4 6 8 10 12 14 16
VVH (V)
Figure 5. VVDDCAP vs. VVH
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
012345
VVP1 (V)
Figure 6. IVP1 vs. VVP1 (VP1 as the Supply)
6
180
160
140
120
100
80
60
40
20
0
0
12345
VVP1 (V)
Figure 7. IVP1 vs. VVP1 (VP1 Not the Supply)
6
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0
2 4 6 8 10 12 14
VVH (V)
Figure 8. IVH vs. VVH (VH as the Supply)
16
350
300
250
200
150
100
50
0
0
12345
VVH (V)
Figure 9. IVH vs. VVH (VH Not the Supply)
6
Rev. 0 | Page 11 of 71

11 Page







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