PDF VS8053b Data sheet ( Hoja de datos )

Número de pieza	VS8053b
Descripción	AUDIO PROCESSOR
Fabricantes	VLSI
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No Preview Available ! VS8053b Datasheet VS8053b - AUDIO PROCESSOR WITH Ogg Vorbis / FLAC / WAV SUPPORT Features Description • Laser-fused version of VS1053b • Decodes Ogg Vorbis; FLAC with software plugin; WAV (PCM + IMA ADPCM) • Encodes Ogg Vorbis w/ software plugin • Encodes stereo IMA ADPCM / PCM • Streaming support for WAV • Unique serial number for user code pro- tection • EarSpeaker Spatial Processing VS8053b is an audio processor with a high performance stereo ADC and DAC. Each de- vice has a factory-programmable unique chip ID that provides a basis for digital rights man- agement or unit identiﬁcation features. VS8053b supports audio formats that do not require a license (Ogg Vorbis, PCM, IMA-ADPCM, FLAC). By using the Ogg Vorbis encoder plu- gin the device can be used to build a high per- formance and low cost digital audio encoder- decoder link. • Bass and treble controls • Operates with a single 12..13 MHz clock VS8053b contains a high-performance, pro- prietary low-power DSP processor core VS_DSP4, • Can also be used with a 24..26 MHz clock • Internal PLL clock multiplier • Low-power operation • High-quality on-chip stereo DAC with no phase error between channels • Zero-cross detection for smooth volume change • Stereo earphone driver capable of driv- ing a 30 Ω load 16 KiB instruction RAM and 16 KiB data RAM for user applications running simultaneously with built-in decoders, serial control and in- put data interfaces, upto 8 general purpose I/O pins, an UART, as well as a high-quality variable-sample-rate stereo ADC (mic, line, line + mic or 2×line) and stereo DAC, fol- lowed by an earphone ampliﬁer and a com- mon voltage buffer. • Quiet power-on and power-off VS8053b receives its input bitstream through • I2S output interface for external DAC a serial input bus, which it listens to as a sys- • Separate voltages for analog, digital, I/O tem slave. The input stream is processed • On-chip RAM for user code and data • Serial control and data interfaces • Can be used as a slave co-processor • SPI ﬂash boot for special applications and passed through a asynchronous sample rate converter and digital volume control to an 18-bit oversampling, multi-bit, sigma-delta DAC. I2S • UART for debugging purposes RCAP • New functions may be added with soft- LINE1 ware and upto 8 GPIO pins • Lead-free RoHS-compliant package LINE2/ MICP MICN MUX MIC amplifier Stereo ADC Stereo DAC Stereo Earphone Driver X ROM LEFT GBUF RIGHT DREQ SO SI SCLK XCS XDCS Serial Data/ Conrol Interface VSDSP4 Processor X RAM Y ROM TX RX OSCI OSCO XRESET TEST UART Clock Instruction ROM Instruction RAM Y RAM GPIO 8 GPIO Version: 1.22, 2014-12-19 1 1 page VS8053b Datasheet LIST OF FIGURES List of Figures 1 Pin conﬁguration, LQFP-48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2 VS8053b in LQFP-48 packaging. . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 Typical connection diagram using LQFP-48. . . . . . . . . . . . . . . . . . . . . . 13 4 SDI in VS10xx Native Mode, single-byte transfer . . . . . . . . . . . . . . . . . . 17 5 SDI in VS10xx Native Mode, multi-byte transfer, X ≥ 1 . . . . . . . . . . . . . . . 17 6 SDI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7 SDI in VS1001 Mode - one byte transfer. Do not use in new designs! . . . . . . . 19 8 SDI in VS1001 Mode - two byte transfer. Do not use in new designs! . . . . . . . 19 9 SCI word read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 10 SCI word write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 11 SCI multiple word write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 12 SPI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 13 Two SCI operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 14 Two SDI bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 15 Two SDI bytes separated by an SCI operation . . . . . . . . . . . . . . . . . . . . 24 16 Data ﬂow of VS8053b. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 17 EarSpeaker externalized sound sources vs. normal inside-the-head sound . . . 29 18 VS8053b ADC and DAC data paths with some data registers . . . . . . . . . . . 59 19 VS8053b ADC and DAC data paths with some data registers . . . . . . . . . . . 60 20 RS232 serial interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 21 I2S interface, 192 kHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Version: 1.22, 2014-12-19 5 5 Page VS8053b Datasheet 5 PACKAGES AND PIN DESCRIPTIONS Pad Name MICP / LINE1 MICN XRESET DGND0 CVDD0 IOVDD0 CVDD1 DREQ GPIO2 / DCLK1 GPIO3 / SDATA1 GPIO6 / I2S_SCLK3 GPIO7 I2S_SDATA3 / XDCS / BSYNC1 IOVDD1 VCO DGND1 XTALO XTALI IOVDD2 DGND2 DGND3 DGND4 XCS CVDD2 GPIO5 / I2S_MCLK3 RX TX SCLK SI SO CVDD3 XTEST GPIO0 LQFP Pin 1 2 3 4 5 6 7 8 9 10 11 12 Pin Type AI AI DI DGND CPWR IOPWR CPWR DO DIO DIO DIO DIO 13 DI 14 IOPWR 15 DO 16 DGND 17 AO 18 AI 19 IOPWR 20 DGND 21 DGND 22 DGND 23 DI 24 CPWR 25 DIO 26 DI 27 DO 28 DI 29 DI 30 DO3 31 CPWR 32 DI 33 DIO GPIO1 GND GPIO4 I2S_LROUT3 AGND0 AVDD0 RIGHT AGND1 AGND2 GBUF 34 35 / 36 37 38 39 40 41 42 DIO DGND DIO APWR APWR AO APWR APWR AO AVDD1 RCAP AVDD2 LEFT AGND3 LINE2 43 APWR 44 AIO 45 APWR 46 AO 47 APWR 48 AI Function Positive differential mic input, self-biasing / Line-in 1 Negative differential mic input, self-biasing Active low asynchronous reset, schmitt-trigger input Core & I/O ground Core power supply I/O power supply Core power supply Data request, input bus General purpose IO 2 / serial input data bus clock General purpose IO 3 / serial data input General purpose IO 6 / I2S_SCLK General purpose IO 7 / I2S_SDATA Data chip select / byte sync I/O power supply For testing only (Clock VCO output) Core & I/O ground Crystal output Crystal input I/O power supply Core & I/O ground Core & I/O ground Core & I/O ground Chip select input (active low) Core power supply General purpose IO 5 / I2S_MCLK UART receive, connect to IOVDD if not used UART transmit Clock for serial bus Serial input Serial output Core power supply Reserved for test, connect to IOVDD Gen. purp. IO 0 (SPIBOOT), use 100 kΩ pull-down resistor2 General purpose IO 1 I/O Ground General purpose IO 4 / I2S_LROUT Analog ground, low-noise reference Analog power supply Right channel output Analog ground Analog ground Common buffer for headphones, do NOT connect to ground! Analog power supply Filtering capacitance for reference Analog power supply Left channel output Analog ground Line-in 2 (right channel) Version: 1.22, 2014-12-19 11 11 Page

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